magathi
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Posts: 3
Utah
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Iam trying to model a simple difference amplifier....
//Verilog-AMS HDL for "test", "pip_difference_amp" "verilogams"
`include "constants.vams" `include "disciplines.vams"
module pip_difference_amp (out,pin,nin); output out; input pin,nin; electrical out, pin,nin; parameter real gain = 1; parameter real td = 0; parameter tt = 0; real diff;
analog begin diff = gain*(V(pin)-V(nin)); V(out)<+transition(diff,td,tt); end
endmodule
This is the error message Iam getting... ERROR (ADEXL-5012): An error occurred while netlisting the testbench on point 1. Could somebody explain what this error means?
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