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urian

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Application of pstb to MDAC
Nov 19^th, 2012, 7:32am

Hi,there.
Recently I'm leanring to use pss+pstb to find the amp performance. The amp is used in a MDAC within a pipeline ADC, and has SC CMFB. I add the cmdmprobe to the amp output and put the amp in the whole MDAC configuration as shown in the pic. Then set the input pac magnitude to 1V and run pss and pstb. But the result is meaningless. I wonder whether I can find the loop gain or PM in a MDAC configuration. As far as I know, the pss is linearized to periodic OP, but the MDAC is controlled with non-overlapped clock and has sample phase followed by amplify phase. So I think there is no steady periodic OP, that's why I have failed to get the correct result, right? If so, how can I get the real loop gain and PM in MDAC configuration？ The spectreRF user guide has no example in this ADC field, Any hint?

Regards
urian

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mdac.jpg

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Ken Kundert Global Moderator Offline Posts: 2386 Silicon Valley	Re: Application of pstb to MDAC Reply #1 - Nov 19^th, 2012, 12:06pm Generally when things go wrong it is in the details, and you have not shown the details, so it is hard to help you. You should be able to apply pstb analysis to your circuit and get meaningful results. For more information on stability analysis, you should take a look at Frank Weidmann's Loop Gain Simulation page. -Ken
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Frank Wiedmann Community Fellow Offline Posts: 678 Munich, Germany	Re: Application of pstb to MDAC Reply #2 - Nov 20^th, 2012, 12:59am The cmdmprobe is obsolete, you should use the diffstbprobe instead. If the circuit has no periodic operating point, the pss analysis will generally not converge.
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urian

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Re: Application of pstb to MDAC
Reply #3 - Nov 20^th, 2012, 7:25am

Hi,ken & Frank
Here is my simulation results and setup. It's a S/H and can also be used as MDAC.The ideal opamp is composed of R, C, and VCVS, VCCS. I also put the cmdmprobe at the output within the opamp.
The pstb stability summary shows meaningless result. But the tran analysis implies that the S/H works well with vsin input, the input frequency is 63.5M and sample rate is 128M. I dont know why the pstb result is as such.

S/H ckt

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mdac_001.jpg

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urian Junior Member Offline Posts: 30	Re: Application of pstb to MDAC Reply #4 - Nov 20^th, 2012, 7:28am ADE setup
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urian Junior Member Offline Posts: 30	Re: Application of pstb to MDAC Reply #5 - Nov 20^th, 2012, 7:29am pstb result
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urian Junior Member Offline Posts: 30	Re: Application of pstb to MDAC Reply #6 - Nov 20^th, 2012, 7:30am tran result
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urian Junior Member Offline Posts: 30	Re: Application of pstb to MDAC Reply #7 - Nov 20^th, 2012, 7:33am sry, I failed to attach all pics in one post.... and all pics look so large... BTW, I havent learnt diffstbprobe before, what's it, and where can I find it? Is it superior to cmdmprobe for fully differential amp case? Regards urina
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Ken Kundert

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Re: Application of pstb to MDAC
Reply #8 - Nov 20^th, 2012, 11:38am

Here are a few comments from looking at what you uploaded.
1. You really don't need to apply the input while running the pstb analysis. Just apply the clock. This will speed up your simulation dramatically.
2. I don't understand the relay that shorts the output.
3. You don't need a port for the input source, a vsource is sufficient.

The pstb analysis complains that it cannot calculate the phase and gain margins. That is your cue to examine the loop gain as a way of understanding what is going wrong.

-Ken

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Frank Wiedmann

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Re: Application of pstb to MDAC
Reply #9 - Nov 21^st, 2012, 5:32am

You can find the diffstbprobe in the analogLib library if you are using a recent version of Cadence Virtuoso. You use it in the same way as the old cmdmprobe. The diffstbprobe uses an improved method that also works for circuits that are not perfectly symmetric.

You should always plot the loop gain and examine its behavior (see http://www.edaboard.com/thread163935.html if you don't know how to do this). Just looking at the gain and phase margins reported in the simulator log is not sufficient.

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urian

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Re: Application of pstb to MDAC
Reply #10 - Nov 21^st, 2012, 8:42am

Ken Kundert wrote on Nov 20^th, 2012, 11:38am:

Here are a few comments from looking at what you uploaded.
1. You really don't need to apply the input while running the pstb analysis. Just apply the clock. This will speed up your simulation dramatically.
2. I don't understand the relay that shorts the output.
3. You don't need a port for the input source, a vsource is sufficient.

-Ken

thx, ken.
1.I set the input to 0 during pstb analysis, so there is no input in fact.
2.The relay works as a reset switch during sample phase.
3.Usually, I use a vsin. The port is learnt from other's ckt, maybe not suitable here.

Frank Wiedmann wrote on Nov 21^st, 2012, 5:32am:

You can find the diffstbprobe in the analogLib library if you are using a recent version of Cadence Virtuoso. You use it in the same way as the old cmdmprobe. The diffstbprobe uses an improved method that also works for circuits that are not perfectly symmetric.

You should always plot the loop gain and examine its behavior (see http://www.edaboard.com/thread163935.html if you don't know how to do this). Just looking at the gain and phase margins reported in the simulator log is not sufficient.

Hi. Frank, the vision of my cadence is not latest enough, so there is no diffstbprobe. Sad

I changed the ideal amp with a real but not well one, then the pstb result is shown as pic. I think this time it works, but I wonder whether the loop gain is reliable, since the open-loop gain is around 500(I test it using traditional way, ac analysis with ideal CMFB, not SC CMFB, can PAC be used instead with SC CMFB to derive open loop gain?), but the loop gain is 50.
Maybe I should learn more about pss pstb pac and re-check the setup and configuration.

Regards
urian

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stb_002.jpg

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Frank Wiedmann

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Re: Application of pstb to MDAC
Reply #11 - Nov 21^st, 2012, 12:06pm

The loop gain looks reasonable now. By the way, the gain magnitude is usually plotted in dB.

I don't know what exactly you mean by open-loop gain, but I don't recommend opening the loop by using large inductors and capacitors. You should be able to use pac analysis with a pac voltage source and two ideal baluns to simulate the voltage loop gain if you absolutely want to verify your result. See the recent thread at http://www.designers-guide.org/Forum/YaBB.pl?num=1352294950 (both pages).

Some Verilog-A models don't pass small signals, see http://www.designers-guide.org/Forum/YaBB.pl?num=1189658426. Maybe you had a similar problem here.

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urian

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Re: Application of pstb to MDAC
Reply #12 - Nov 21^st, 2012, 8:41pm

hi,Frank
The open-loop gain (I think it is also called DC gain)is that there is no DM feedback loop, it has only CMFB under fully differential case. For my ckt, I simulate it by AC analysis and get 54dB low frequency gain.
Then I measure it using tran analysis, that is output voltage divided by input voltage, e.g, 480mv/800uv, both of which are the voltage of amp. It's about 54dB also. So I think the amp gain is indeed around 54dB.
And in S/H configuration, the feedback factor is around 1/2 ~ 1/3, so I think the loop gain is approximately 45dB. That why I am doubting of the result.
BTW , when you want to plot loop gain magnitude and phase together, the magnitude has no dB20 modifier option, so you can only see the absolute value. And in my second testbench, there is no verilogA block since I have replaced the ideal amp with a real one.

Regards
urian

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