// Fixed frequency oscillators // // Version 1b, 23 October 2006 // // Ken Kundert // // Downloaded from The Designer's Guide (www.designers-guide.org). // Post any questions to www.designers-guide.org/Forum `include "disciplines.vams" `include "constants.vams" // // Fixed frequency oscillator // module osc1 (out); output out; voltage out; // output signal parameter real freq=1 from (0:inf); // output frequency parameter real vl=-1; // high output voltage parameter real vh=1; // low output voltage parameter real tt=0.01/freq from (0:inf); // transition time of output integer n; real next; analog begin @(initial_step) begin next = 0.5/freq + \$abstime; end @(timer(next)) begin n = !n; next = next + 0.5/freq; end V(out) <+ transition(n ? vh : vl, 0, tt); end endmodule // // Fixed frequency oscillator with white accumulating jitter. // // Accumulating jitter is the jitter associated with a free-running oscillator. // module osc2 (out); output out; voltage out; // output signal parameter real freq=1 from (0:inf); // output frequency parameter real vl=-1; // high output voltage parameter real vh=1; // low output voltage parameter real tt=0.01/freq from (0:inf); // transition time of output parameter real jitter=0 from [0:0.1/freq); // white period jitter integer n, seed; real next, dT; analog begin @(initial_step) begin seed = 286; next = 0.5/freq + \$abstime; end @(timer(next)) begin n = !n; dT = jitter*\$rdist_normal(seed,0,1); next = next + 0.5/freq + `M_SQRT1_2*dT; end V(out) <+ transition(n ? vh : vl, 0, tt); end endmodule // // Fixed-frequency oscillator with white synchronous jitter. // // Synchronous jitter is the jitter associated with a driven circuit. // module osc3 (out); output out; voltage out; // output signal parameter real freq=1 from (0:inf); // output frequency parameter real vl=-1; // high output voltage parameter real vh=1; // low output voltage parameter real tt=0.01/freq from (0:inf); // transition time of output parameter real jitter=0 from [0:0.1/freq); // white edge-to-edge jitter integer n, Seed; real next, dT, dt, SD; analog begin @(initial_step) begin Seed = -459; SD = jitter; next = 0.5/freq + \$abstime; end @(timer(next + dt)) begin n = !n; dt = SD*\$rdist_normal(Seed,0,1); next = next + 0.5/freq; end V(out) <+ transition(n ? vh : vl, 0, tt); end endmodule // // Fixed-frequency oscillator with white accumulating and synchronous jitter. // // Accumulating jitter is the jitter associated with a free-running oscillator. // Synchronous jitter is the jitter associated with a driven circuit. // module osc4 (out); output out; voltage out; // output signal parameter real freq=1 from (0:inf); // output frequency parameter real vl=-1; // high output voltage parameter real vh=1; // low output voltage parameter real tt=0.01/freq from (0:inf); // transition time of output parameter real acc_jitter=0 from [0:0.1/freq); // white period jitter parameter real sync_jitter=0 from [0:0.1/freq); // white edge-to-edge jitter integer n, accSeed, syncSeed; real next, dT, dt, accSD, syncSD; analog begin @(initial_step) begin accSeed = 286; syncSeed = -459; accSD = acc_jitter*`M_SQRT1_2; syncSD = sync_jitter; next = 0.5/freq + \$abstime; end @(timer(next + dt)) begin n = !n; dT = accSD*\$rdist_normal(accSeed,0,1); dt = syncSD*\$rdist_normal(syncSeed,0,1); next = next + 0.5/freq + dT; end V(out) <+ transition(n ? vh : vl, 0, tt); end endmodule