// Phase-Frequency Detector with Charge Pump // // pfd_cp1: a simple three state phase-frequency detector // pfd_cp2: a phase-frequency detector that exhibits Gaussian synchronous jitter // // Both charge pumps include an output clamp that encourages the output voltage to // fall within the rails. // // Version 1e, 3 August 2010 // // Ken Kundert (ken@designers-guide.com) // // Downloaded from The Designer's Guide Community (www.designers-guide.org). // Post any questions to www.designers-guide.org/Forum `include "disciplines.vams" `include "constants.vams" // // This model exhibits no jitter // module pfd_cp1 (out, ref, fb); output out; electrical out; // current output input ref; voltage ref; // positive input (edge triggered) input fb; voltage fb; // inverting input (edge triggered) parameter real iout=100u; // maximum output current parameter real vh=+1; // input voltage in high state parameter real vl=-1; // input voltage in low state parameter real vth=(vh+vl)/2; // threshold voltage at input parameter integer dir=1 from [-1:1] exclude 0; // dir=1 for positive edge trigger // dir=-1 for negative edge trigger parameter real tt=1n from (0:inf); // transition time of output signal parameter real td=0 from [0:inf); // average delay from input to output parameter real rclamp=100 from (0:inf); // output clamp resistance integer state; analog begin // Implement phase detector @(cross(V(ref)-vth, dir)) if (state > -1) state = state - 1; @(cross(V(fb)-vth, dir)) if (state < 1) state = state + 1; // Implement charge pump I(out) <+ transition(iout*state, td, tt); // Implement output clamp (optional) if (V(out) > vh) I(out) <+ (V(out) - vh)/rclamp; else if (V(out) < vl) I(out) <+ (V(out) - vl)/rclamp; // Add gmin to output to avoid convergence issues (optional) I(out) <+ V(out)/1T; end endmodule // // This model exhibits white Gaussian synchronous jitter // module pfd_cp2 (out, ref, fb); output out; electrical out; // current output input ref; voltage ref; // positive input (edge triggered) input fb; voltage fb; // inverting input (edge triggered) parameter real iout=100u; // maximum output current parameter real vh=+1; // input voltage in high state parameter real vl=-1; // input voltage in low state parameter real vth=(vh+vl)/2; // threshold voltage at input parameter integer dir=1 from [-1:1] exclude 0; // dir=1 for positive edge trigger // dir=-1 for negative edge trigger parameter real tt=1n from (0:inf); // transition time of output signal parameter real td=0 from (0:inf); // average delay from input to output parameter real jitter=0 from [0:td/5); // white edge-to-edge jitter parameter real ttol=1p from (0:td/5); // time tolerance, recommend ttol << jitter parameter real rclamp=100 from (0:inf); // output clamp resistance integer state, seed; real dt; analog begin @(initial_step) seed = 716; // Implement phase detector @(cross(V(ref)-vth, dir, ttol)) begin if (state > -1) state = state - 1; dt = jitter*\$rdist_normal(seed,0,1); end @(cross(V(fb)-vth, dir, ttol)) begin if (state < 1) state = state + 1; dt = jitter*\$rdist_normal(seed,0,1); end // Implement charge pump I(out) <+ transition(iout*state, td + dt, tt); // Implement output clamp (optional) if (V(out) > vh) I(out) <+ (V(out) - vh)/rclamp; else if (V(out) < vl) I(out) <+ (V(out) - vl)/rclamp; // Add gmin to output to avoid convergence issues (optional) I(out) <+ V(out)/1T; end endmodule