// Idealized sample and holds // // Version 1b, 17 July 03 // // Ken Kundert // designers-guide.org's Guide (www.designers-guide.org). // Post any questions to www.designers-guide.org/Forum `include "disciplines.vams" // // Self-clocked (periodic) sample and hold // module sh1(Pout, Nout, Pin, Nin); input Pin, Nin; voltage Pin, Nin; // input port output Pout, Nout; voltage Pout, Nout; // output port parameter real period=1 from (0:inf); // sampling period (s) parameter real toff=0 from [0:inf); // offset time for sampling (s) parameter real td=0 from [0:inf); // delay from sampling to output (s) parameter real tt=period/100 from (0:inf); // duration of output transitions (s) integer n; real tstop, save; analog begin // Determine the sample time n = (\$abstime - toff) / period; tstop = n*period + toff; // Sample the input @(timer(tstop) or initial_step) save = V(Pin,Nin); // Produce output with well-controlled transitions V(Pout,Nout) <+ transition(save, td, tt); end endmodule // // Externally-clocked sample and hold // module sh2(Pout, Nout, Pin, Nin, clk); input Pin, Nin; voltage Pin, Nin; // input port output Pout, Nout; voltage Pout, Nout; // output port input clk; voltage clk; // trigger parameter real td = 0 from [0:inf); // delay from sampling to output (s) parameter real tt = 0 from [0:inf); // transition time of output signals (s) parameter real vth = 0; // threshold voltage at trigger input (V) parameter integer dir = +1 from [-1:+1] exclude 0; // if dir=+1, rising clock edge triggers flip flop // if dir=-1, falling clock edge triggers flip flop real save; analog begin // Sample the input @(cross(V(clk) - vth, dir) or initial_step) save = V(Pin,Nin); // Produce output with well-controlled transitions V(Pout,Nout) <+ transition(save, td, tt); end endmodule