// Generated for: spectre
// Generated on: Dec 27 12:52:52 2009
// Design library name: SHA
// Design cell name: tb_SHA_noise
// Design view name: config
simulator lang=spectre
global 0
include "/apps/EDAs/cadence/IC5141/tools/dfII/samples/artist/ahdlLib/quantity.spectre"
parameters Ron=20
include "/net/dell2900b/export/smic2009/library/SMIC65nm/pdk/SPDK65LL_121825_1TM_OD33_CDS_v0.1/smic65ll_121825_1tm_1P7M_20090814/models/spectre/l0065ll_io25_od33_v1p0_spe.lib" section=mom_tt
include "/net/dell2900b/export/smic2009/library/SMIC65nm/pdk/SPDK65LL_121825_1TM_OD33_CDS_v0.1/smic65ll_121825_1tm_1P7M_20090814/models/spectre/l0065ll_io25_od33_v1p0_spe.lib" section=res_tt
include "/net/dell2900b/export/smic2009/library/SMIC65nm/pdk/SPDK65LL_121825_1TM_OD33_CDS_v0.1/smic65ll_121825_1tm_1P7M_20090814/models/spectre/l0065ll_io25_od33_v1p0_spe.lib" section=tt

// Library name: analogLib
// Cell name: ideal_balun
// View name: schematic
// Inherited view list: spectre cmos_sch cmos.sch schematic veriloga ahdl
subckt ideal_balun d c p n
    K1 (d 0 c n) transformer n1=2
    K0 (d 0 p c) transformer n1=2
ends ideal_balun
// End of subcircuit definition.

// Library name: SHA
// Cell name: GIBIAS_SH_V1
// View name: schematic
// Inherited view list: spectre cmos_sch cmos.sch schematic veriloga ahdl
subckt GIBIAS_SH_V1 GIBIN GNDA IBA IBSH10 IBSH11 IBSH2 VDDA
    NM3 (net072 net072 GNDA GNDA) n12ll w=(12u) l=1u as=1.425p ad=1.2p \
        ps=15.2375u pd=12.2u sa=2e-6 sb=2e-6 m=(1)*(8)
    NM2 (IBSH2 net072 GNDA GNDA) n12ll w=(12u) l=1u as=1.425p ad=1.2p \
        ps=15.2375u pd=12.2u sa=2e-6 sb=2e-6 m=(1)*(8)
    NM1 (IBSH2 IBA GNDA GNDA) n12ll w=(12u) l=1u as=1.425p ad=1.2p \
        ps=15.2375u pd=12.2u sa=2e-6 sb=2e-6 m=(1)*(8)
    NM0 (IBA IBA GNDA GNDA) n12ll w=(12u) l=1u as=1.425p ad=1.2p \
        ps=15.2375u pd=12.2u sa=2e-6 sb=2e-6 m=(1)*(8)
    NM4 (GNDA GNDA net99 GNDA) n12ll w=(12u) l=1u as=2.1p ad=1.2p \
        ps=24.35u pd=12.2u sa=5e-6 sb=5e-6 m=(1)*(2)
    NM5 (GNDA GNDA net91 GNDA) n12ll w=(12u) l=1u as=2.1p ad=1.2p \
        ps=24.35u pd=12.2u sa=5e-6 sb=5e-6 m=(1)*(2)
    NM6 (GNDA net99 GNDA GNDA) n12ll w=(5u) l=5u as=505.282f ad=505.282f \
        ps=5.27254u pd=5.27254u sa=5e-6 sb=5e-6 m=(1)*(71)
    Mb0 (GIBIN GIBIN net99 GNDA) n12ll w=(12u) l=1u as=1.425p ad=1.2p \
        ps=15.2375u pd=12.2u sa=5e-6 sb=5e-6 m=(1)*(8)
    mb2 (net91 net99 GNDA GNDA) n12ll w=(12u) l=1u as=1.425p ad=1.2p \
        ps=15.2375u pd=12.2u sa=5e-6 sb=5e-6 m=(1)*(8)
    mb3 (net95 GIBIN net91 GNDA) n12ll w=(12u) l=1u as=1.425p ad=1.2p \
        ps=15.2375u pd=12.2u sa=5e-6 sb=5e-6 m=(1)*(8)
    Mb1 (net99 net99 GNDA GNDA) n12ll w=(12u) l=1u as=1.425p ad=1.2p \
        ps=15.2375u pd=12.2u sa=5e-6 sb=5e-6 m=(1)*(8)
    PM1 (net072 net95 VDDA VDDA) p12ll w=(14u) l=1u as=1.45833p ad=1.4p \
        ps=14.9861u pd=14.2u sa=5e-6 sb=5e-6 m=(1)*(36)
    mb4 (net95 net95 VDDA VDDA) p12ll w=(14u) l=1u as=1.53125p ad=1.4p \
        ps=15.9688u pd=14.2u sa=5e-6 sb=5e-6 m=(1)*(16)
    mb6 (IBSH11 net95 VDDA VDDA) p12ll w=(14u) l=1u as=1.53125p ad=1.4p \
        ps=15.9688u pd=14.2u sa=5e-6 sb=5e-6 m=(1)*(16)
    mb5 (IBSH10 net95 VDDA VDDA) p12ll w=(14u) l=1u as=1.53125p ad=1.4p \
        ps=15.9688u pd=14.2u sa=5e-6 sb=5e-6 m=(1)*(16)
ends GIBIAS_SH_V1
// End of subcircuit definition.

// Library name: SHA
// Cell name: AN_SH_V2
// View name: schematic
// Inherited view list: spectre cmos_sch cmos.sch schematic veriloga ahdl
subckt AN_SH_V2 GNDA VB1 VB2 VB3 VB4 VCMN VDDA VIN VIP VON VOP
    NM0 (GNDA VDDA GNDA GNDA) n12ll w=(4u) l=1u as=700f ad=700f ps=8.35u \
        pd=8.35u sa=5e-6 sb=5e-6 m=(1)*(1)
    M10 (VOP VB3 net97 GNDA) n12ll w=(5u) l=200n as=537.5f ad=500f \
        ps=5.715u pd=5.2u sa=2e-6 sb=2e-6 m=(1)*(20)
    M4 (net_1 VB4 GNDA GNDA) n12ll w=(5u) l=200n as=541.667f ad=500f \
        ps=5.77222u pd=5.2u sa=2e-6 sb=2e-6 m=(1)*(18)
    M12 (net97 VB4 GNDA GNDA) n12ll w=(5u) l=200n as=575f ad=500f ps=6.23u \
        pd=5.2u sa=5e-6 sb=5e-6 m=(1)*(10)
    M11 (net93 VB4 GNDA GNDA) n12ll w=(5u) l=200n as=575f ad=500f ps=6.23u \
        pd=5.2u sa=5e-6 sb=5e-6 m=(1)*(10)
    M9 (VON VB3 net93 GNDA) n12ll w=(5u) l=200n as=537.5f ad=500f \
        ps=5.715u pd=5.2u sa=2e-6 sb=2e-6 m=(1)*(20)
    M2 (net_2 VIP net_1 GNDA) n12ll w=(5u) l=100n as=531.25f ad=500f \
        ps=5.62917u pd=5.2u sa=2e-6 sb=2e-6 m=(1)*(24)
    M3 (VDDA VCMN net_1 GNDA) n12ll w=(5u) l=100n as=562.5f ad=500f \
        ps=6.05833u pd=5.2u sa=2e-6 sb=2e-6 m=(1)*(12)
    M1 (net_3 VIN net_1 GNDA) n12ll w=(5u) l=100n as=531.25f ad=500f \
        ps=5.62917u pd=5.2u sa=2e-6 sb=2e-6 m=(1)*(24) degradation=no
    M6 (net_3 VB1 VDDA VDDA) p12ll w=(5u) l=200n as=513.393f ad=500f \
        ps=5.38393u pd=5.2u sa=2e-6 sb=2e-6 m=(1)*(56)
    M8 (VOP VB2 net_3 VDDA) p12ll w=(5u) l=200n as=509.146f ad=509.146f \
        ps=5.32561u pd=5.32561u sa=2e-6 sb=2e-6 m=(1)*(41)
    M7 (VON VB2 net_2 VDDA) p12ll w=(5u) l=200n as=509.146f ad=509.146f \
        ps=5.32561u pd=5.32561u sa=2e-6 sb=2e-6 m=(1)*(41)
    M5 (net_2 VB1 VDDA VDDA) p12ll w=(5u) l=200n as=513.393f ad=500f \
        ps=5.38393u pd=5.2u sa=2e-6 sb=2e-6 m=(1)*(56)
ends AN_SH_V2
// End of subcircuit definition.

// Library name: SHA
// Cell name: AP_SH_V2
// View name: schematic
// Inherited view list: spectre cmos_sch cmos.sch schematic veriloga ahdl
subckt AP_SH_V2 GNDA NW_AP VB1 VB2 VB3 VB4 VCMP VCND_AP VCNU_AP VCPD_AP \
        VCPU_AP VDDA VIN VIP VON VOP
    NM3 (GNDA GNDA VCPD_AP GNDA) n12ll w=(5u) l=200n as=875f ad=500f \
        ps=10.35u pd=5.2u sa=2e-6 sb=2e-6 m=(1)*(2)
    NM2 (GNDA GNDA VCND_AP GNDA) n12ll w=(5u) l=200n as=875f ad=500f \
        ps=10.35u pd=5.2u sa=2e-6 sb=2e-6 m=(1)*(2)
    M10 (VOP VB3 VCPD_AP GNDA) n12ll w=(5u) l=200n as=534.091f ad=500f \
        ps=5.66818u pd=5.2u sa=2e-6 sb=2e-6 m=(1)*(22)
    M12 (VCPD_AP VB4 GNDA GNDA) n12ll w=(5u) l=200n as=534.091f ad=500f \
        ps=5.66818u pd=5.2u sa=2e-6 sb=2e-6 m=(1)*(22)
    M11 (VCND_AP VB4 GNDA GNDA) n12ll w=(5u) l=200n as=534.091f ad=500f \
        ps=5.66818u pd=5.2u sa=2e-6 sb=2e-6 m=(1)*(22)
    M9 (VON VB3 VCND_AP GNDA) n12ll w=(5u) l=200n as=534.091f ad=500f \
        ps=5.66818u pd=5.2u sa=2e-6 sb=2e-6 m=(1)*(22)
    PM3 (VDDA VDDA VCPU_AP VDDA) p12ll w=(4u) l=200n as=700f ad=400f \
        ps=8.35u pd=4.2u sa=2e-6 sb=2e-6 m=(1)*(2)
    PM2 (VDDA VDDA VCNU_AP VDDA) p12ll w=(4u) l=200n as=700f ad=400f \
        ps=8.35u pd=4.2u sa=2e-6 sb=2e-6 m=(1)*(2)
    M6 (VCPU_AP VB1 VDDA VDDA) p12ll w=(5u) l=200n as=510.714f ad=510.714f \
        ps=5.34714u pd=5.34714u sa=2e-6 sb=2e-6 m=(1)*(35)
    M8 (VOP VB2 VCPU_AP VDDA) p12ll w=(5u) l=200n as=509.146f ad=509.146f \
        ps=5.32561u pd=5.32561u sa=2e-6 sb=2e-6 m=(1)*(41)
    M7 (VON VB2 VCNU_AP VDDA) p12ll w=(5u) l=200n as=509.146f ad=509.146f \
        ps=5.32561u pd=5.32561u sa=2e-6 sb=2e-6 m=(1)*(41)
    M5 (VCNU_AP VB1 VDDA VDDA) p12ll w=(5u) l=200n as=510.714f ad=510.714f \
        ps=5.34714u pd=5.34714u sa=2e-6 sb=2e-6 m=(1)*(35)
    M1 (NW_AP VB1 VDDA VDDA) p12ll w=(5u) l=200n as=510.417f ad=500f \
        ps=5.34306u pd=5.2u sa=2e-6 sb=2e-6 m=(1)*(72)
    M2 (VCND_AP VIP NW_AP NW_AP) p12ll w=(5u) l=100n as=525f ad=500f \
        ps=5.54333u pd=5.2u sa=2e-6 sb=2e-6 m=(1)*(30)
    M4 (GNDA VCMP NW_AP NW_AP) p12ll w=(5u) l=100n as=553.571f ad=500f \
        ps=5.93571u pd=5.2u sa=2e-6 sb=2e-6 m=(1)*(14)
    M3 (VCPD_AP VIN NW_AP NW_AP) p12ll w=(5u) l=100n as=525f ad=500f \
        ps=5.54333u pd=5.2u sa=2e-6 sb=2e-6 m=(1)*(30)
ends AP_SH_V2
// End of subcircuit definition.

// Library name: SHA
// Cell name: IBIAS1_SH_V2
// View name: schematic
// Inherited view list: spectre cmos_sch cmos.sch schematic veriloga ahdl
subckt IBIAS1_SH_V2 GNDA IBSH10 IBSH11 VB1 VB2 VB3 VB4 VCMN VCMP VDDA
    NM30 (GNDA GNDA net0110 GNDA) n12ll w=(5u) l=200n as=875f ad=500f \
        ps=10.35u pd=5.2u sa=2e-6 sb=2e-6 m=(1)*(2)
    NM32 (GNDA GNDA net0141 GNDA) n12ll w=(5u) l=200n as=875f ad=500f \
        ps=10.35u pd=5.2u sa=2e-6 sb=2e-6 m=(1)*(2)
    NM33 (GNDA GNDA net187 GNDA) n12ll w=(5u) l=200n as=875f ad=500f \
        ps=10.35u pd=5.2u sa=2e-6 sb=2e-6 m=(1)*(2)
    NM34 (GNDA GNDA net183 GNDA) n12ll w=(5u) l=200n as=875f ad=500f \
        ps=10.35u pd=5.2u sa=2e-6 sb=2e-6 m=(1)*(2)
    NM35 (GNDA GNDA VCMP GNDA) n12ll w=(5u) l=200n as=875f ad=500f \
        ps=10.35u pd=5.2u sa=2e-6 sb=2e-6 m=(1)*(2)
    NM31 (GNDA GNDA net0126 GNDA) n12ll w=(5u) l=200n as=875f ad=500f \
        ps=10.35u pd=5.2u sa=2e-6 sb=2e-6 m=(1)*(2)
    NM36 (net0110 GNDA GNDA GNDA) n12ll w=(6.1u) l=1u as=1.0675p \
        ad=1.0675p ps=12.55u pd=12.55u sa=2e-6 sb=2e-6 m=(1)*(1)
    NM10 (net0110 IBSH10 GNDA GNDA) n12ll w=(6.5u) l=1u as=1.1375p ad=650f \
        ps=13.35u pd=6.7u sa=2e-6 sb=2e-6 m=(1)*(2)
    NM9 (IBSH10 IBSH10 net0110 GNDA) n12ll w=(5u) l=200n as=534.091f \
        ad=534.091f ps=5.66818u pd=5.66818u sa=2e-6 sb=2e-6 m=(1)*(11)
    NM3 (net0126 IBSH11 GNDA GNDA) n12ll w=(5u) l=200n as=625f ad=500f \
        ps=6.91667u pd=5.2u sa=2e-6 sb=2e-6 m=(1)*(6)
    M12 (VB3 VB3 net183 GNDA) n12ll w=(5u) l=200n as=534.091f ad=534.091f \
        ps=5.66818u pd=5.66818u sa=2e-6 sb=2e-6 m=(1)*(11)
    NM8 (VCMP VB4 GNDA GNDA) n12ll w=(5u) l=200n as=625f ad=500f \
        ps=6.91667u pd=5.2u sa=2e-6 sb=2e-6 m=(1)*(6)
    NM7 (VB4 IBSH10 VCMP GNDA) n12ll w=(5u) l=200n as=534.091f ad=534.091f \
        ps=5.66818u pd=5.66818u sa=2e-6 sb=2e-6 m=(1)*(11)
    NM2 (net0141 IBSH11 GNDA GNDA) n12ll w=(5u) l=200n as=625f ad=500f \
        ps=6.91667u pd=5.2u sa=2e-6 sb=2e-6 m=(1)*(6)
    NM6 (net187 IBSH11 GNDA GNDA) n12ll w=(5u) l=200n as=625f ad=500f \
        ps=6.91667u pd=5.2u sa=2e-6 sb=2e-6 m=(1)*(6)
    M13 (net183 VB3 GNDA GNDA) n12ll w=(5u) l=740n as=875f ad=500f \
        ps=10.35u pd=5.2u sa=2e-6 sb=2e-6 m=(1)*(2)
    NM4 (IBSH11 IBSH10 net0126 GNDA) n12ll w=(5u) l=200n as=534.091f \
        ad=534.091f ps=5.66818u pd=5.66818u sa=2e-6 sb=2e-6 m=(1)*(11)
    NM1 (VB1 IBSH10 net0141 GNDA) n12ll w=(5u) l=200n as=534.091f \
        ad=534.091f ps=5.66818u pd=5.66818u sa=2e-6 sb=2e-6 m=(1)*(11)
    NM5 (VB2 IBSH10 net187 GNDA) n12ll w=(5u) l=200n as=534.091f \
        ad=534.091f ps=5.66818u pd=5.66818u sa=2e-6 sb=2e-6 m=(1)*(11)
    PM18 (VDDA VDDA VCMN VDDA) p12ll w=(5u) l=200n as=875f ad=500f \
        ps=10.35u pd=5.2u sa=2e-6 sb=2e-6 m=(1)*(2)
    PM15 (VDDA VDDA net0335 VDDA) p12ll w=(5u) l=200n as=875f ad=500f \
        ps=10.35u pd=5.2u sa=2e-6 sb=2e-6 m=(1)*(2)
    PM16 (VDDA VDDA net134 VDDA) p12ll w=(2.5u) l=200n as=437.5f ad=250f \
        ps=5.35u pd=2.7u sa=2e-6 sb=2e-6 m=(1)*(2)
    PM17 (VDDA VDDA net122 VDDA) p12ll w=(2.5u) l=200n as=437.5f ad=250f \
        ps=5.35u pd=2.7u sa=2e-6 sb=2e-6 m=(1)*(2)
    PM0 (VB2 VB2 net134 VDDA) p12ll w=(5u) l=200n as=515f ad=515f \
        ps=5.406u pd=5.406u sa=2e-6 sb=2e-6 m=(1)*(25)
    PM3 (VB3 VB2 net122 VDDA) p12ll w=(5u) l=200n as=515f ad=515f \
        ps=5.406u pd=5.406u sa=2e-6 sb=2e-6 m=(1)*(25)
    PM6 (VB4 VB2 VCMN VDDA) p12ll w=(5u) l=200n as=515f ad=515f ps=5.406u \
        pd=5.406u sa=2e-6 sb=2e-6 m=(1)*(25)
    PM1 (net134 VB2 VDDA VDDA) p12ll w=(5u) l=330n as=687.5f ad=500f \
        ps=7.775u pd=5.2u sa=2e-6 sb=2e-6 m=(1)*(4)
    PM5 (VCMN VB1 VDDA VDDA) p12ll w=(5u) l=200n as=541.667f ad=500f \
        ps=5.77222u pd=5.2u sa=2e-6 sb=2e-6 m=(1)*(18)
    PM4 (net122 VB1 VDDA VDDA) p12ll w=(5u) l=200n as=541.667f ad=500f \
        ps=5.77222u pd=5.2u sa=2e-6 sb=2e-6 m=(1)*(18)
    M0 (VB1 VB2 net0335 VDDA) p12ll w=(5u) l=200n as=515f ad=515f \
        ps=5.406u pd=5.406u sa=2e-6 sb=2e-6 m=(1)*(25)
    M1 (net0335 VB1 VDDA VDDA) p12ll w=(5u) l=200n as=541.667f ad=500f \
        ps=5.77222u pd=5.2u sa=2e-6 sb=2e-6 m=(1)*(18)
ends IBIAS1_SH_V2
// End of subcircuit definition.

// Library name: SHA
// Cell name: IBIAS2_SH_V2
// View name: schematic
// Inherited view list: spectre cmos_sch cmos.sch schematic veriloga ahdl
subckt IBIAS2_SH_V2 VCM1 VDDA VST2
    PM2 (VDDA VDDA net8 VDDA) p12ll w=(5u) l=100n as=875f ad=500f \
        ps=10.35u pd=5.2u sa=2e-6 sb=2e-6 m=(1)*(2)
    PM1 (net8 VST2 VDDA VDDA) p12ll w=(5u) l=200n as=518.75f ad=500f \
        ps=5.4575u pd=5.2u sa=2e-6 sb=2e-6 m=(1)*(40)
    PM0 (VST2 VCM1 net8 VDDA) p12ll w=(5u) l=100n as=518.75f ad=500f \
        ps=5.4575u pd=5.2u sa=2e-6 sb=2e-6 m=(1)*(40)
ends IBIAS2_SH_V2
// End of subcircuit definition.

// Library name: SHA
// Cell name: OTA_SH_V2
// View name: schematic
// Inherited view list: spectre cmos_sch cmos.sch schematic veriloga ahdl
subckt OTA_SH_V2 GNDA IBSH10 IBSH11 NW1 NW2 VAPN VAPP VB4 VCM1 VCND VCNU \
        VCPD VCPU VDDA VFB1 VFB2 VIN VIP VO1N VO1P VON VOP VST2
    I1 (GNDA VB1 VB2 VB3 VB4 VCMN VDDA VCNU VCPU net0160 VANP) AN_SH_V2
    I2 (GNDA net0315 VB1 VB2 VB3 VB4 VCMP net0314 net0313 net0312 net0311 \
        VDDA VCND VCPD net0167 VAPP) AP_SH_V2
    IPRB0 (net0167 VAPN) iprobe
    IPRB1 (net0160 VANN) iprobe
    I21 (GNDA IBSH10 IBSH11 VB1 VB2 VB3 VB4 VCMN VCMP VDDA) IBIAS1_SH_V2
    I3 (VCM1 VDDA VST2) IBIAS2_SH_V2
    M9b (VCND VB4 GNDA GNDA) n12ll w=(5u) l=200n as=575f ad=500f ps=6.23u \
        pd=5.2u sa=2e-6 sb=2e-6 m=(1)*(10)
    M9a (VCND VFB1 GNDA GNDA) n12ll w=(5u) l=200n as=509.375f ad=500f \
        ps=5.32875u pd=5.2u sa=2e-6 sb=2e-6 m=(1)*(80)
    NM4 (GNDA VB4 GNDA GNDA) n12ll w=(5u) l=5u as=511.364f ad=511.364f \
        ps=5.35606u pd=5.35606u m=(1)*(33)
    M7 (VO1N VAPP VCND GNDA) n12ll w=(5u) l=100n as=513.393f ad=500f \
        ps=5.38393u pd=5.2u sa=2e-6 sb=2e-6 m=(2)*(56)
    NM2 (GNDA VB1 GNDA GNDA) n12ll w=(5u) l=5u as=526.786f ad=500f \
        ps=5.56786u pd=5.2u m=(1)*(28)
    NM3 (GNDA VB3 GNDA GNDA) n12ll w=(5u) l=5u as=526.786f ad=500f \
        ps=5.56786u pd=5.2u m=(1)*(28)
    M18 (VOP VB4 GNDA GNDA) n12ll w=(5u) l=200n as=511.719f ad=500f \
        ps=5.36094u pd=5.2u sa=2e-6 sb=2e-6 m=(1)*(64)
    M10b (VCPD VB4 GNDA GNDA) n12ll w=(5u) l=200n as=575f ad=500f ps=6.23u \
        pd=5.2u sa=2e-6 sb=2e-6 m=(1)*(10)
    M8 (VO1P VAPN VCPD GNDA) n12ll w=(5u) l=100n as=513.393f ad=500f \
        ps=5.38393u pd=5.2u sa=2e-6 sb=2e-6 m=(2)*(56)
    M10a (VCPD VFB1 GNDA GNDA) n12ll w=(5u) l=200n as=509.375f ad=500f \
        ps=5.32875u pd=5.2u sa=2e-6 sb=2e-6 m=(1)*(80)
    M21 (VON VB4 GNDA GNDA) n12ll w=(5u) l=200n as=511.719f ad=500f \
        ps=5.36094u pd=5.2u sa=2e-6 sb=2e-6 m=(1)*(64)
    M14 (VOP VO1N NW2 NW2) p12ll w=(5u) l=100n as=520.833f ad=500f \
        ps=5.48611u pd=5.2u sa=2e-6 sb=2e-6 m=(4)*(36)
    M3 (VCNU VB1 VDDA VDDA) p12ll w=(5u) l=200n as=515.625f ad=500f \
        ps=5.41458u pd=5.2u sa=2e-6 sb=2e-6 m=(4)*(48)
    M2a (VCND VIP NW1 NW1) p12ll w=(5u) l=200n as=513.393f ad=500f \
        ps=5.38393u pd=5.2u sa=2e-6 sb=2e-6 m=(2)*(56)
    M1a (VCPD VIN NW1 NW1) p12ll w=(5u) l=200n as=513.393f ad=500f \
        ps=5.38393u pd=5.2u sa=2e-6 sb=2e-6 m=(2)*(56)
    PM6 (VDDA VCMP VDDA VDDA) p12ll w=(5u) l=5u as=553.571f ad=500f \
        ps=5.93571u pd=5.2u m=(1)*(14)
    M17 (VON VO1P NW2 NW2) p12ll w=(5u) l=100n as=520.833f ad=500f \
        ps=5.48611u pd=5.2u sa=2e-6 sb=2e-6 m=(4)*(36)
    PM9 (VDDA VST2 VDDA VDDA) p12ll w=(5u) l=5u as=593.75f ad=500f \
        ps=6.4875u pd=5.2u m=(1)*(8)
    PM7 (VDDA VB2 VDDA VDDA) p12ll w=(5u) l=5u as=541.667f ad=500f \
        ps=5.77222u pd=5.2u m=(1)*(18)
    M0 (NW1 VB1 VDDA VDDA) p12ll w=(5u) l=200n as=518.75f ad=500f \
        ps=5.4575u pd=5.2u sa=2e-6 sb=2e-6 m=(4)*(40)
    M6 (VO1P VANN VCPU VCPU) p12ll w=(5u) l=100n as=508.333f ad=508.333f \
        ps=5.31444u pd=5.31444u sa=2e-6 sb=2e-6 m=(2)*(45)
    M5 (VO1N VANP VCNU VCNU) p12ll w=(5u) l=100n as=508.333f ad=508.333f \
        ps=5.31444u pd=5.31444u sa=2e-6 sb=2e-6 m=(2)*(45)
    M13 (NW2 VFB2 VDDA VDDA) p12ll w=(5u) l=200n as=518.75f ad=500f \
        ps=5.4575u pd=5.2u sa=2e-6 sb=2e-6 m=(8)*(40)
    M11 (NW2 VST2 VDDA VDDA) p12ll w=(5u) l=200n as=518.75f ad=500f \
        ps=5.4575u pd=5.2u sa=2e-6 sb=2e-6 m=(2)*(40)
    M4 (VCPU VB1 VDDA VDDA) p12ll w=(5u) l=200n as=515.625f ad=500f \
        ps=5.41458u pd=5.2u sa=2e-6 sb=2e-6 m=(4)*(48)
    C3 (VCNU VOP) mom_ckt lr=13.49u nr=72
    C5 (VCNU VOP) mom_ckt lr=13.49u nr=72
    C29 (VCPD VON) mom_ckt lr=13.49u nr=72
    C9 (VCND VOP) mom_ckt lr=13.49u nr=72
    C31 (VANP GNDA) mom_ckt lr=10u nr=80
    C8 (VCNU VOP) mom_ckt lr=13.49u nr=72
    C2 (VCND VOP) mom_ckt lr=13.49u nr=72
    C30 (VCPD VON) mom_ckt lr=13.49u nr=72
    C32 (net0160 GNDA) mom_ckt lr=10u nr=80
    C14 (VCPU VON) mom_ckt lr=13.49u nr=72
    C18 (VCPD VON) mom_ckt lr=13.49u nr=72
    C28 (VCND VOP) mom_ckt lr=13.49u nr=72
    C27 (VCND VOP) mom_ckt lr=13.49u nr=72
    C35 (VCPD VON) mom_ckt lr=13.49u nr=72
    C7 (net0167 GNDA) mom_ckt lr=10u nr=60
    C6 (VAPP GNDA) mom_ckt lr=10u nr=60
    C4 (VCNU VOP) mom_ckt lr=13.49u nr=72
    C1 (VCNU VOP) mom_ckt lr=13.49u nr=72
    C22 (VCPU VON) mom_ckt lr=13.49u nr=72
    C13 (VCPU VON) mom_ckt lr=13.49u nr=72
    C10 (VCND VOP) mom_ckt lr=13.49u nr=72
    C21 (VCPU VON) mom_ckt lr=13.49u nr=72
    C15 (VCPU VON) mom_ckt lr=13.49u nr=72
    C17 (VCPD VON) mom_ckt lr=13.49u nr=72
ends OTA_SH_V2
// End of subcircuit definition.

// Library name: PADC12B50M_V2
// Cell name: CSW2XC
// View name: schematic
// Inherited view list: spectre cmos_sch cmos.sch schematic veriloga ahdl
subckt CSW2XC CK CKN GND IN OUT VDD
    PM0 (IN CKN OUT VDD) p12ll w=(5u) l=90n as=875f ad=500f ps=10.35u \
        pd=5.2u m=(1)*(2)
    NM0 (OUT CK IN GND) n12ll w=(5u) l=90n as=875f ad=500f ps=10.35u \
        pd=5.2u m=(1)*(2)
ends CSW2XC
// End of subcircuit definition.

// Library name: SHA
// Cell name: CMFB_SC0X
// View name: schematic
// Inherited view list: spectre cmos_sch cmos.sch schematic veriloga ahdl
subckt CMFB_SC0X CK1 CK1N CK2 CK2N GNDA VB VCMO VDDA VFB VON VOP
    I16 (CK2 CK2N GNDA VOP net36 VDDA) CSW2XC
    I17 (CK1 CK1N GNDA net72 VOP VDDA) CSW2XC
    I19 (CK1 CK1N GNDA net42 VB VDDA) CSW2XC
    I18 (CK1 CK1N GNDA net36 VCMO VDDA) CSW2XC
    I26 (CK1 CK1N GNDA net30 VCMO VDDA) CSW2XC
    I25 (CK2 CK2N GNDA VON net30 VDDA) CSW2XC
    I20 (CK2 CK2N GNDA VFB net42 VDDA) CSW2XC
    I21 (CK1 CK1N GNDA net54 VFB VDDA) CSW2XC
    I22 (CK2 CK2N GNDA VB net54 VDDA) CSW2XC
    I24 (CK1 CK1N GNDA net66 VON VDDA) CSW2XC
    I23 (CK2 CK2N GNDA VCMO net66 VDDA) CSW2XC
    I15 (CK2 CK2N GNDA VCMO net72 VDDA) CSW2XC
    C6 (net54 net66) mom_ckt lr=9u nr=12
    C7 (net42 net30) mom_ckt lr=9u nr=12
    C5 (net42 net36) mom_ckt lr=9u nr=12
    C4 (VFB VOP) mom_ckt lr=9u nr=12
    C8 (VFB VON) mom_ckt lr=9u nr=12
    C2 (net54 net72) mom_ckt lr=9u nr=12
ends CMFB_SC0X
// End of subcircuit definition.

// Library name: SHA
// Cell name: BS_ST0S
// View name: schematic
// Inherited view list: spectre cmos_sch cmos.sch schematic veriloga ahdl
subckt BS_ST0S CK CKN GNDA VCMI VDDA VIN VIP
    C1 (net3 net5) mom_ckt lr=13.49u nr=72
    C3 (net3 net5) mom_ckt lr=13.49u nr=72
    C2 (net3 net5) mom_ckt lr=13.49u nr=72
    C0 (net3 net5) mom_ckt lr=13.49u nr=72
    NM20 (VIP net6 VCMI GNDA) n12ll w=(2.5u) l=90n as=437.5f ad=250f \
        ps=5.35u pd=2.7u m=(1)*(2)
    NM19 (VCMI net6 net5 GNDA) n12ll w=(2.5u) l=90n as=437.5f ad=250f \
        ps=5.35u pd=2.7u m=(1)*(2)
    NM18 (VCMI net6 VIN GNDA) n12ll w=(2.5u) l=90n as=437.5f ad=250f \
        ps=5.35u pd=2.7u m=(1)*(2)
    NM17 (VIN net6 VIP GNDA) n12ll w=(2.5u) l=90n as=268.75f ad=250f \
        ps=2.965u pd=2.7u m=(1)*(20)
    NM12 (met4 net6 net5 GNDA) n12ll w=(1u) l=90n as=175f ad=175f ps=2.35u \
        pd=2.35u m=(1)*(1)
    NM13 (net7 CKN GNDA GNDA) n12ll w=(2.5u) l=90n as=343.75f ad=250f \
        ps=4.025u pd=2.7u m=(1)*(4)
    NM14 (net6 VDDA net7 GNDA) n12ll w=(2.5u) l=90n as=343.75f ad=250f \
        ps=4.025u pd=2.7u m=(1)*(4)
    NM15 (net5 CKN GNDA GNDA) n12ll w=(2.5u) l=90n as=437.5f ad=437.5f \
        ps=5.35u pd=5.35u m=(1)*(1)
    NM16 (met4 CK net5 GNDA) n12ll w=(1u) l=90n as=175f ad=175f ps=2.35u \
        pd=2.35u m=(1)*(1)
    PM4 (met4 CK VDDA VDDA) p12ll w=(2.5u) l=90n as=437.5f ad=437.5f \
        ps=5.35u pd=5.35u m=(1)*(1)
    PM5 (VDDA CKN net7 VDDA) p12ll w=(2.5u) l=90n as=437.5f ad=437.5f \
        ps=5.35u pd=5.35u m=(1)*(1)
    PM6 (net6 met4 net3 net3) p12ll w=(2.5u) l=90n as=437.5f ad=250f \
        ps=5.35u pd=2.7u m=(1)*(2)
    PM7 (VDDA net6 net3 net3) p12ll w=(2.5u) l=90n as=437.5f ad=250f \
        ps=5.35u pd=2.7u m=(1)*(2)
ends BS_ST0S
// End of subcircuit definition.

// Library name: SHA
// Cell name: BS_ST0R
// View name: schematic
// Inherited view list: spectre cmos_sch cmos.sch schematic veriloga ahdl
subckt BS_ST0R CK CKN GNDA VCMO VDDA VRST
    C0 (net3 net5) mom_ckt lr=13.49u nr=72
    NM13 (net5 CKN GNDA GNDA) n12ll w=(2.5u) l=90n as=437.5f ad=437.5f \
        ps=5.35u pd=5.35u m=(1)*(1)
    NM9 (VCMO VRST net5 GNDA) n12ll w=(2.5u) l=90n as=437.5f ad=250f \
        ps=5.35u pd=2.7u m=(1)*(2)
    NM14 (met4 CK net5 GNDA) n12ll w=(1u) l=90n as=175f ad=175f ps=2.35u \
        pd=2.35u m=(1)*(1)
    NM12 (VRST VDDA net7 GNDA) n12ll w=(2.5u) l=90n as=343.75f ad=250f \
        ps=4.025u pd=2.7u m=(1)*(4)
    NM11 (net7 CKN GNDA GNDA) n12ll w=(2.5u) l=90n as=343.75f ad=250f \
        ps=4.025u pd=2.7u m=(1)*(4)
    NM10 (met4 VRST net5 GNDA) n12ll w=(1u) l=90n as=175f ad=175f ps=2.35u \
        pd=2.35u m=(1)*(1)
    PM7 (VDDA VRST net3 net3) p12ll w=(2.5u) l=90n as=437.5f ad=250f \
        ps=5.35u pd=2.7u m=(1)*(2)
    PM4 (met4 CK VDDA VDDA) p12ll w=(2.5u) l=90n as=437.5f ad=437.5f \
        ps=5.35u pd=5.35u m=(1)*(1)
    PM6 (VRST met4 net3 net3) p12ll w=(2.5u) l=90n as=437.5f ad=250f \
        ps=5.35u pd=2.7u m=(1)*(2)
    PM5 (VDDA CKN net7 VDDA) p12ll w=(2.5u) l=90n as=437.5f ad=437.5f \
        ps=5.35u pd=5.35u m=(1)*(1)
ends BS_ST0R
// End of subcircuit definition.

// Library name: SHA
// Cell name: BS_ST0F
// View name: schematic
// Inherited view list: spectre cmos_sch cmos.sch schematic veriloga ahdl
subckt BS_ST0F CK CKN GNDA VDDA VIN VOUT
    C0 (net3 net5) mom_ckt lr=13.49u nr=72
    NM10 (met4 net6 net5 GNDA) n12ll w=(1u) l=90n as=175f ad=175f ps=2.35u \
        pd=2.35u m=(1)*(1)
    NM11 (net7 CKN GNDA GNDA) n12ll w=(2.5u) l=90n as=343.75f ad=250f \
        ps=4.025u pd=2.7u m=(1)*(4)
    NM12 (net6 VDDA net7 GNDA) n12ll w=(2.5u) l=90n as=343.75f ad=250f \
        ps=4.025u pd=2.7u m=(1)*(4)
    NM14 (met4 CK net5 GNDA) n12ll w=(1u) l=90n as=175f ad=175f ps=2.35u \
        pd=2.35u m=(1)*(1)
    NM9 (VIN net6 net5 GNDA) n12ll w=(2.5u) l=90n as=312.5f ad=312.5f \
        ps=3.58333u pd=3.58333u m=(1)*(3)
    NM15 (VOUT net6 VIN GNDA) n12ll w=(2.5u) l=90n as=281.25f ad=250f \
        ps=3.14167u pd=2.7u m=(1)*(12)
    NM13 (net5 CKN GNDA GNDA) n12ll w=(2.5u) l=90n as=437.5f ad=437.5f \
        ps=5.35u pd=5.35u m=(1)*(1)
    PM5 (VDDA CKN net7 VDDA) p12ll w=(2.5u) l=90n as=437.5f ad=437.5f \
        ps=5.35u pd=5.35u m=(1)*(1)
    PM6 (net6 met4 net3 net3) p12ll w=(2.5u) l=90n as=437.5f ad=250f \
        ps=5.35u pd=2.7u m=(1)*(2)
    PM4 (met4 CK VDDA VDDA) p12ll w=(2.5u) l=90n as=437.5f ad=437.5f \
        ps=5.35u pd=5.35u m=(1)*(1)
    PM7 (VDDA net6 net3 net3) p12ll w=(2.5u) l=90n as=437.5f ad=250f \
        ps=5.35u pd=2.7u m=(1)*(2)
ends BS_ST0F
// End of subcircuit definition.

// Library name: PADC12B50M_V2
// Cell name: CSW4XC
// View name: schematic
// Inherited view list: spectre cmos_sch cmos.sch schematic veriloga ahdl
subckt CSW4XC CK CKN GND IN OUT VDD
    PM0 (IN CKN OUT VDD) p12ll w=(5u) l=90n as=687.5f ad=500f ps=7.775u \
        pd=5.2u m=(1)*(4)
    NM0 (OUT CK IN GND) n12ll w=(4.5u) l=90n as=618.75f ad=450f ps=7.025u \
        pd=4.7u m=(1)*(4)
ends CSW4XC
// End of subcircuit definition.

// Library name: SHA
// Cell name: CMFB_SC2X
// View name: schematic
// Inherited view list: spectre cmos_sch cmos.sch schematic veriloga ahdl
subckt CMFB_SC2X CK1 CK1N CK2 CK2N GNDA VB VCMO VDDA VFB VON VOP
    C10 (VFB VON) mom_ckt lr=9u nr=20
    C11 (net42 net30) mom_ckt lr=9u nr=20
    C6 (net54 net72) mom_ckt lr=9u nr=20
    C8 (net42 net36) mom_ckt lr=9u nr=20
    C7 (VFB VOP) mom_ckt lr=9u nr=20
    C9 (net54 net66) mom_ckt lr=9u nr=20
    I16 (CK2 CK2N GNDA VOP net36 VDDA) CSW4XC
    I17 (CK1 CK1N GNDA net72 VOP VDDA) CSW4XC
    I19 (CK1 CK1N GNDA net42 VB VDDA) CSW4XC
    I18 (CK1 CK1N GNDA net36 VCMO VDDA) CSW4XC
    I26 (CK1 CK1N GNDA net30 VCMO VDDA) CSW4XC
    I25 (CK2 CK2N GNDA VON net30 VDDA) CSW4XC
    I20 (CK2 CK2N GNDA VFB net42 VDDA) CSW4XC
    I21 (CK1 CK1N GNDA net54 VFB VDDA) CSW4XC
    I22 (CK2 CK2N GNDA VB net54 VDDA) CSW4XC
    I24 (CK1 CK1N GNDA net66 VON VDDA) CSW4XC
    I23 (CK2 CK2N GNDA VCMO net66 VDDA) CSW4XC
    I15 (CK2 CK2N GNDA VCMO net72 VDDA) CSW4XC
ends CMFB_SC2X
// End of subcircuit definition.

// Library name: SHA
// Cell name: BS_ST0I_LL
// View name: schematic
// Inherited view list: spectre cmos_sch cmos.sch schematic veriloga ahdl
subckt BS_ST0I_LL CK CKN GNDA VBK VDDA VIN VOUT
    C5 (net_3 net_5) mom_ckt lr=13.49u nr=72
    C4 (net_3 net_5) mom_ckt lr=13.49u nr=72
    C2 (net_3 net_5) mom_ckt lr=13.49u nr=72
    C3 (VBK VNW) mom_ckt lr=9u nr=24
    C0 (net_3 net_5) mom_ckt lr=13.49u nr=72
    M0 (VOUT net_6 VIN VBK) n12ll w=(2.5u) l=90n as=254.687f ad=250f \
        ps=2.76625u pd=2.7u m=(1)*(80)
    M15 (VDDA VDDA VNW GNDA) n12ll w=(2.5u) l=90n as=343.75f ad=250f \
        ps=4.025u pd=2.7u m=(1)*(4)
    M1 (VBK net_6 VIN VBK) n12ll w=(2.5u) l=90n as=343.75f ad=250f \
        ps=4.025u pd=2.7u m=(1)*(4)
    M2 (VBK CKN GNDA GNDA) n12ll w=(2.5u) l=90n as=343.75f ad=250f \
        ps=4.025u pd=2.7u m=(1)*(4)
    M10 (VIN net_6 net_5 VBK) n12ll w=(2.5u) l=90n as=437.5f ad=250f \
        ps=5.35u pd=2.7u m=(1)*(2)
    M8 (net_4 net_6 net_5 GNDA) n12ll w=(1u) l=90n as=175f ad=175f \
        ps=2.35u pd=2.35u m=(1)*(1)
    M12 (net_7 CKN GNDA GNDA) n12ll w=(2.5u) l=90n as=343.75f ad=250f \
        ps=4.025u pd=2.7u m=(1)*(4)
    M9 (net_6 VDDA net_7 GNDA) n12ll w=(2.5u) l=90n as=343.75f ad=250f \
        ps=4.025u pd=2.7u m=(1)*(4)
    M5 (net_5 CKN GNDA GNDA) n12ll w=(2.5u) l=90n as=437.5f ad=437.5f \
        ps=5.35u pd=5.35u m=(1)*(1)
    M3 (net_4 CK net_5 GNDA) n12ll w=(1u) l=90n as=175f ad=175f ps=2.35u \
        pd=2.35u m=(1)*(1)
    M4 (net_4 CK VDDA VDDA) p12ll w=(2.5u) l=90n as=437.5f ad=437.5f \
        ps=5.35u pd=5.35u m=(1)*(1)
    M11 (VDDA CKN net_7 VDDA) p12ll w=(2.5u) l=90n as=437.5f ad=437.5f \
        ps=5.35u pd=5.35u m=(1)*(1)
    M7 (net_6 net_4 net_3 net_3) p12ll w=(2.5u) l=90n as=437.5f ad=250f \
        ps=5.35u pd=2.7u m=(1)*(2)
    M6 (VDDA net_6 net_3 net_3) p12ll w=(2.5u) l=90n as=437.5f ad=250f \
        ps=5.35u pd=2.7u m=(1)*(2)
ends BS_ST0I_LL
// End of subcircuit definition.

// Library name: PADC12B50M_V2
// Cell name: INV8X
// View name: schematic
// Inherited view list: spectre cmos_sch cmos.sch schematic veriloga ahdl
subckt INV8X GNDD VDDD VIN VOUT
    NM0 (VOUT VIN GNDD GNDD) n12ll w=(600n) l=90n as=71.25f ad=60f \
        ps=987.5n pd=800n m=(1)*(8)
    PM0 (VOUT VIN VDDD VDDD) p12ll w=(1.5u) l=90n as=178.125f ad=150f \
        ps=2.1125u pd=1.7u m=(1)*(8)
ends INV8X
// End of subcircuit definition.

// Library name: PADC12B50M_V2
// Cell name: NAND2_2X
// View name: schematic
// Inherited view list: spectre cmos_sch cmos.sch schematic veriloga ahdl
subckt NAND2_2X A B GNDD VDDD Z
    NM0 (Z A net13 GNDD) n12ll w=(600n) l=90n as=82.5f ad=60f ps=1.175u \
        pd=800n m=(1)*(4)
    NM1 (net13 B GNDD GNDD) n12ll w=(600n) l=90n as=82.5f ad=60f ps=1.175u \
        pd=800n m=(1)*(4)
    PM1 (Z B VDDD VDDD) p12ll w=(1.5u) l=90n as=262.5f ad=150f ps=3.35u \
        pd=1.7u m=(1)*(2)
    PM0 (Z A VDDD VDDD) p12ll w=(1.5u) l=90n as=262.5f ad=150f ps=3.35u \
        pd=1.7u m=(1)*(2)
ends NAND2_2X
// End of subcircuit definition.

// Library name: PADC12B50M_V2
// Cell name: INV2X
// View name: schematic
// Inherited view list: spectre cmos_sch cmos.sch schematic veriloga ahdl
subckt INV2X GNDD VDDD VIN VOUT
    NM0 (VOUT VIN GNDD GNDD) n12ll w=(600n) l=90n as=105f ad=60f ps=1.55u \
        pd=800n m=(1)*(2)
    PM0 (VOUT VIN VDDD VDDD) p12ll w=(1.5u) l=90n as=262.5f ad=150f \
        ps=3.35u pd=1.7u m=(1)*(2)
ends INV2X
// End of subcircuit definition.

// Library name: PADC12B50M_V2
// Cell name: INV4X
// View name: schematic
// Inherited view list: spectre cmos_sch cmos.sch schematic veriloga ahdl
subckt INV4X GNDD VDDD VIN VOUT
    PM0 (VOUT VIN VDDD VDDD) p12ll w=(1.5u) l=90n as=206.25f ad=150f \
        ps=2.525u pd=1.7u m=(1)*(4)
    NM0 (VOUT VIN GNDD GNDD) n12ll w=(600n) l=90n as=82.5f ad=60f \
        ps=1.175u pd=800n m=(1)*(4)
ends INV4X
// End of subcircuit definition.

// Library name: PADC12B50M_V2
// Cell name: INV16X
// View name: schematic
// Inherited view list: spectre cmos_sch cmos.sch schematic veriloga ahdl
subckt INV16X GNDD VDDD VIN VOUT
    NM0 (VOUT VIN GNDD GNDD) n12ll w=(600n) l=90n as=65.625f ad=60f \
        ps=893.75n pd=800n m=(1)*(16)
    PM0 (VOUT VIN VDDD VDDD) p12ll w=(1.5u) l=90n as=164.063f ad=150f \
        ps=1.90625u pd=1.7u m=(1)*(16)
ends INV16X
// End of subcircuit definition.

// Library name: PADC12B50M_V2
// Cell name: INV32X
// View name: schematic
// Inherited view list: spectre cmos_sch cmos.sch schematic veriloga ahdl
subckt INV32X GNDD VDDD VIN VOUT
    NM0 (VOUT VIN GNDD GNDD) n12ll w=(600n) l=90n as=62.8125f ad=60f \
        ps=846.875n pd=800n m=(1)*(32)
    PM0 (VOUT VIN VDDD VDDD) p12ll w=(1.5u) l=90n as=157.031f ad=150f \
        ps=1.80312u pd=1.7u m=(1)*(32)
ends INV32X
// End of subcircuit definition.

// Library name: PADC12B50M_V2
// Cell name: INV64X
// View name: schematic
// Inherited view list: spectre cmos_sch cmos.sch schematic veriloga ahdl
subckt INV64X GNDD VDDD VIN VOUT
    NM0 (VOUT VIN GNDD GNDD) n12ll w=(600n) l=90n as=61.4063f ad=60f \
        ps=823.438n pd=800n m=(1)*(64)
    PM0 (VOUT VIN VDDD VDDD) p12ll w=(1.5u) l=90n as=153.516f ad=150f \
        ps=1.75156u pd=1.7u m=(1)*(64)
ends INV64X
// End of subcircuit definition.

// Library name: PADC12B50M_V2
// Cell name: INV81X
// View name: schematic
// Inherited view list: spectre cmos_sch cmos.sch schematic veriloga ahdl
subckt INV81X GNDD VDDD VIN VOUT
    NM0 (VOUT VIN GNDD GNDD) n12ll w=(600n) l=90n as=60.5556f ad=60.5556f \
        ps=809.259n pd=809.259n m=(1)*(81)
    PM0 (VOUT VIN VDDD VDDD) p12ll w=(1.5u) l=90n as=151.389f ad=151.389f \
        ps=1.72037u pd=1.72037u m=(1)*(81)
ends INV81X
// End of subcircuit definition.

// Library name: PADC12B50M_V2
// Cell name: NAND2_4X
// View name: schematic
// Inherited view list: spectre cmos_sch cmos.sch schematic veriloga ahdl
subckt NAND2_4X A B GNDD VDDD Z
    NM0 (Z A net13 GNDD) n12ll w=(600n) l=90n as=71.25f ad=60f ps=987.5n \
        pd=800n m=(1)*(8)
    NM1 (net13 B GNDD GNDD) n12ll w=(600n) l=90n as=71.25f ad=60f \
        ps=987.5n pd=800n m=(1)*(8)
    PM1 (Z B VDDD VDDD) p12ll w=(1.5u) l=90n as=206.25f ad=150f ps=2.525u \
        pd=1.7u m=(1)*(4)
    PM0 (Z A VDDD VDDD) p12ll w=(1.5u) l=90n as=206.25f ad=150f ps=2.525u \
        pd=1.7u m=(1)*(4)
ends NAND2_4X
// End of subcircuit definition.

// Library name: PADC12B50M_V2
// Cell name: CLOCK2_V2
// View name: schematic
// Inherited view list: spectre cmos_sch cmos.sch schematic veriloga ahdl
subckt CLOCK2_V2 CK1 CK1N CK1P CK1PN CK2 CK2N CK2P CK2PN CKEXT GNDD VDDD
    I79 (GNDD VDDD net171 net61) INV8X
    I10 (GNDD VDDD net155 net57) INV8X
    I68 (GNDD VDDD net171 net53) INV8X
    I45 (GNDD VDDD net95 net49) INV8X
    I44 (GNDD VDDD net155 net45) INV8X
    I34 (GNDD VDDD net91 net41) INV8X
    I63 (GNDD VDDD net99 net37) INV8X
    I74 (GNDD VDDD net53 net33) INV8X
    I77 (GNDD VDDD net87 net29) INV8X
    I66 (GNDD VDDD net83 net25) INV8X
    I27 (GNDD VDDD net79 net21) INV8X
    I46 (GNDD VDDD net45 net17) INV8X
    I2 (GNDD VDDD net111 net13) INV8X
    I73 (AT net75 GNDD VDDD net0185) NAND2_2X
    I3 (BT net13 GNDD VDDD net66) NAND2_2X
    I21 (GNDD VDDD CKEXT net75) INV2X
    I1 (GNDD VDDD CKEXT net111) INV4X
    I80 (GNDD VDDD net0185 net107) INV4X
    I4 (GNDD VDDD net66 net103) INV4X
    I75 (GNDD VDDD net53 net99) INV4X
    I217 (GNDD VDDD net45 net95) INV4X
    I35 (GNDD VDDD net79 net91) INV4X
    I69 (GNDD VDDD net372 net87) INV4X
    I76 (GNDD VDDD net87 net83) INV4X
    I28 (GNDD VDDD net377 net79) INV4X
    I58 (GNDD VDDD net175 net187) INV16X
    I210 (GNDD VDDD net179 BT) INV16X
    I209 (GNDD VDDD net187 net179) INV16X
    I64 (GNDD VDDD net61 net175) INV16X
    I78 (GNDD VDDD net279 net171) INV16X
    I8 (GNDD VDDD net57 net167) INV16X
    I212 (GNDD VDDD net159 net163) INV16X
    I9 (GNDD VDDD net167 net159) INV16X
    I11 (GNDD VDDD net251 net155) INV16X
    I60 (GNDD VDDD net25 net151) INV16X
    I42 (GNDD VDDD net49 net147) INV16X
    I33 (GNDD VDDD net41 net143) INV16X
    I57 (GNDD VDDD net37 net139) INV16X
    I65 (GNDD VDDD net107 net135) INV16X
    I67 (GNDD VDDD net29 net131) INV16X
    I62 (GNDD VDDD net33 net127) INV16X
    I25 (GNDD VDDD net21 net123) INV16X
    I5 (GNDD VDDD net103 net119) INV16X
    I43 (GNDD VDDD net17 net115) INV16X
    I224 (GNDD VDDD net135 net303) INV32X
    I223 (GNDD VDDD net303 net299) INV32X
    I222 (GNDD VDDD net119 net295) INV32X
    I221 (GNDD VDDD net295 net291) INV32X
    I96 (GNDD VDDD net275 net287) INV32X
    I93 (GNDD VDDD net247 net283) INV32X
    I59 (GNDD VDDD net287 net279) INV32X
    I95 (GNDD VDDD net271 net275) INV32X
    I89 (GNDD VDDD net267 net271) INV32X
    I90 (GNDD VDDD net263 net267) INV32X
    I92 (GNDD VDDD net259 net263) INV32X
    I91 (GNDD VDDD net255 net259) INV32X
    I84 (GNDD VDDD net299 net255) INV32X
    I6 (GNDD VDDD net283 net251) INV32X
    I94 (GNDD VDDD net243 net247) INV32X
    I88 (GNDD VDDD net239 net243) INV32X
    I87 (GNDD VDDD net235 net239) INV32X
    I85 (GNDD VDDD net231 net235) INV32X
    I86 (GNDD VDDD net227 net231) INV32X
    I81 (GNDD VDDD net291 net227) INV32X
    I211 (GNDD VDDD net163 AT) INV32X
    I41 (GNDD VDDD net115 net219) INV32X
    I40 (GNDD VDDD net147 net215) INV32X
    I32 (GNDD VDDD net143 net211) INV32X
    I26 (GNDD VDDD net123 net207) INV32X
    I53 (GNDD VDDD net139 net203) INV32X
    I56 (GNDD VDDD net127 net199) INV32X
    I61 (GNDD VDDD net131 net195) INV32X
    I54 (GNDD VDDD net151 net191) INV32X
    I31 (GNDD VDDD net211 net335) INV64X
    I38 (GNDD VDDD net215 net331) INV64X
    I39 (GNDD VDDD net219 net327) INV64X
    I23 (GNDD VDDD net207 net323) INV64X
    I52 (GNDD VDDD net199 net319) INV64X
    I49 (GNDD VDDD net203 net315) INV64X
    I55 (GNDD VDDD net195 net311) INV64X
    I50 (GNDD VDDD net191 net307) INV64X
    I37 (GNDD VDDD net327 CK1P) INV81X
    I51 (GNDD VDDD net311 CK2) INV81X
    I48 (GNDD VDDD net319 CK2P) INV81X
    I36 (GNDD VDDD net331 CK1PN) INV81X
    I24 (GNDD VDDD net323 CK1) INV81X
    I219 (GNDD VDDD net307 CK2N) INV81X
    I218 (GNDD VDDD net335 CK1N) INV81X
    I220 (GNDD VDDD net315 CK2PN) INV81X
    I22 (AT net251 GNDD VDDD net377) NAND2_4X
    I225 (BT net279 GNDD VDDD net372) NAND2_4X
ends CLOCK2_V2
// End of subcircuit definition.

// Library name: SHA
// Cell name: SHA_V1
// View name: schematic
// Inherited view list: spectre cmos_sch cmos.sch schematic veriloga ahdl
subckt SHA_V1 CK1P CKSH GIBIN GNDA GNDAG GNDD GNDDG IBA VCM1 VCMI VCMO \
        VDDA VDDAG VDDD VDDDG VIN VIP VON VOP
    I22 (GIBIN GNDA IBA IBSH10 IBSH11 VST2 VDDA) GIBIAS_SH_V1
    I6 (GNDA IBSH10 IBSH11 NW1 NW2 VAPN VAPP VB4 VCM1 VCND VCNU VCPD VCPU \
        VDDA VFB1 VFB2 net0151 net108 VO1N VO1P VON VOP VST2) OTA_SH_V2
    PM0 (VDDA VCMI VDDA VDDA) p12ll w=(5u) l=5u as=526.786f ad=500f \
        ps=5.56786u pd=5.2u m=(1)*(28)
    I19 (CK1 CK1N CK2 CK2N GNDD VB4 VCM1 VDDD VFB1 VO1N VO1P) CMFB_SC0X
    I10 (CK2P CK2PN GNDA VCMI VDDA net108 net0151) BS_ST0S
    I18 (CK2 CK2N GNDA VCMO VDDA VRST) BS_ST0R
    I17 (CK1 CK1N GNDA VDDA net95 VOP) BS_ST0F
    I16 (CK1 CK1N GNDA VDDA net101 VON) BS_ST0F
    I20 (CK1 CK1N CK2 CK2N GNDD VST2 VCMO VDDD VFB2 VON VOP) CMFB_SC2X
    I11 (CK2 CK2N GNDA net065 VDDA VIN net95) BS_ST0I_LL
    I9 (CK2 CK2N GNDA net0127 VDDA VIP net101) BS_ST0I_LL
    I7 (CK1 CK1N CK1P CK1PN CK2 CK2N CK2P CK2PN CKSH GNDD VDDD) CLOCK2_V2
    C23 (net108 GNDA) mom_ckt lr=10u nr=90
    C15 (net108 net101) mom_ckt lr=13.49u nr=72
    C9 (net0151 net95) mom_ckt lr=13.49u nr=72
    C8 (net0151 net95) mom_ckt lr=13.49u nr=72
    C20 (net0151 net95) mom_ckt lr=13.49u nr=72
    C13 (net108 net101) mom_ckt lr=13.49u nr=72
    C5 (net108 net101) mom_ckt lr=13.49u nr=72
    C6 (net108 net101) mom_ckt lr=13.49u nr=72
    C21 (net0151 net95) mom_ckt lr=13.49u nr=72
    C4 (net108 net101) mom_ckt lr=13.49u nr=72
    C10 (net0151 net95) mom_ckt lr=13.49u nr=72
    C16 (net108 net101) mom_ckt lr=13.49u nr=72
    C18 (net0151 net95) mom_ckt lr=13.49u nr=72
    C22 (net0151 net95) mom_ckt lr=13.49u nr=72
    C24 (net0151 GNDA) mom_ckt lr=10u nr=90
    C19 (net0151 net95) mom_ckt lr=13.49u nr=72
    C17 (net108 net101) mom_ckt lr=13.49u nr=72
    C14 (net108 net101) mom_ckt lr=13.49u nr=72
    C7 (net0151 net95) mom_ckt lr=13.49u nr=72
    C0 (net108 net101) mom_ckt lr=13.49u nr=72
    NM3 (net0127 CK2N net065 GNDA) n12ll w=(2.5u) l=90n as=343.75f ad=250f \
        ps=4.025u pd=2.7u m=(1)*(4)
    NM4 (GNDA GNDA GNDA GNDA) n12ll w=(5u) l=5u as=505.769f ad=505.769f \
        ps=5.27923u pd=5.27923u m=(1)*(65)
    NM5 (GNDA GNDA GNDA GNDA) n12ll w=(5u) l=5u as=505.769f ad=505.769f \
        ps=5.27923u pd=5.27923u m=(1)*(65)
    NM0 (VO1N VRST VO1P GNDA) n12ll w=(2.5u) l=90n as=287.5f ad=287.5f \
        ps=3.23u pd=3.23u sa=1e-6 sb=1e-6 m=(1)*(5)
    NM1 (VON VRST VOP GNDA) n12ll w=(2.5u) l=90n as=287.5f ad=287.5f \
        ps=3.23u pd=3.23u sa=1e-6 sb=1e-6 m=(1)*(5)
ends SHA_V1
// End of subcircuit definition.

// Library name: SHA
// Cell name: tb_SHA_noise
// View name: schematic
// Inherited view list: spectre cmos_sch cmos.sch schematic veriloga ahdl
I10 (VOP VON VOP1 VON1) sh
I9 (net021 VCMI VINP VINN) ideal_balun
VIN (net021 GNDA) vsource dc=0 type=dc freq=5M ampl=300m pacmag=1 mag=1 \
        xfmag=1 fundname="Fsig"
I0 (CK1P CKSH GIBIN GNDA net016 GNDD net015 GNDA VCM1 VCMI VCMO VDDA \
        net014 VDDD net013 VINN VINP VON1 VOP1) SHA_V1
R1 (VOP1 net033) resistor r=20 isnoisy=no
R0 (VON1 net035) resistor r=20 isnoisy=no
C7 (net033 GNDA) capacitor c=4.5p
C8 (net035 GNDA) capacitor c=4.5p
V0 (CKSH GNDD) vsource type=pulse val0=0 val1=1.2 period=1/50M rise=10p \
        fall=10p width=1/100M
I4 (VDDA GIBIN) isource dc=200u type=dc
V9 (VCM1 GNDA) vsource dc=500.0m type=dc
V11 (VCMI GNDA) vsource dc=500.0m type=dc
V4 (VDDD GNDD) vsource dc=1.2 type=dc
V1 (GNDD 0) vsource dc=0 type=dc
V3 (GNDA 0) vsource dc=0 type=dc
V10 (VCMO GNDA) vsource dc=500.0m type=dc
V2 (VDDA GNDA) vsource dc=1.2 type=dc
simulatorOptions options reltol=1e-5 vabstol=3e-8 iabstol=1e-13 temp=27 \
    tnom=27 scalem=1.0 scale=1.0 gmin=1e-12 rforce=1 maxnotes=5 maxwarns=5 \
    digits=5 cols=80 pivrel=1e-3 sensfile="../psf/sens.output" \
    dochecklimit=yes checklimitdest=psf 
dcOpCheckLimit checklimit checkallasserts=yes severity=none
dcOp dc write="spectre.dc" maxiters=150 maxsteps=10000 annotate=status
dcOpInfo info what=oppoint where=rawfile
pss  pss  fund=50M  harms=0  errpreset=moderate  tstab=400n
+    saveinit=yes  tstabmethod=gear2only  maxacfreq=3G  annotate=status
pnoise  (  VOP  VON  )  pnoise  start=0.5M  stop=300M  step=0.5M
+       maxsideband=10  iprobe=VIN  refsideband=0  annotate=status
modelParameter info what=models where=rawfile
element info what=inst where=rawfile
outputParameter info what=output where=rawfile
designParamVals info what=parameters where=rawfile
primitives info what=primitives where=rawfile
subckts info what=subckts  where=rawfile
asserts info what=assert  where=rawfile
saveOptions options save=allpub
ahdl_include "/net/dell2900b/export/smic2009/ghShu/SHA/sh/veriloga/veriloga.va"
