proc SCHEMATIC_project_synth {} {
make output -name out -origin {1720 70}
make name_net -name vin -origin {1450 70}
make name_net -name div_val -origin {1420 410}
make name_net -name sd_in -origin {550 410}
make name_net -name ref -origin {280 70}
make step_in -name xi10 -vend in_gl+delta_gl -vstart in_gl -tstep step_time_gl -origin {460 410}
make output -name noiseout -origin {1720 150}
make name_net -name down -origin {440 130}
make name_net -name up -origin {450 70}
make name_net -name iup -origin {710 70}
make name_net -name idown -origin {720 130}
make sub2 -name xi2 -origin {790 70}
make vco -name xi1 -freq 26e6 -kvco 1 -origin {180 90}
make vco_and_divider_with_noise -name xi4 -fc 900e6 -kv 50e6 -foffset 20e6 -noise_at_foffset -165 -origin {1550 110}
make tristate_pfd -name xi11 -reset_delay 2.5e-9 -origin {350 90}
make sd_modulator -name xi9 -order 3 -origin {710 430}
make rcfilter -name xi5 -fo 500e3 -origin {1140 70}
make rcfilter -name xi6 -fo 1e6 -origin {1330 70}
make leadlagfilter -name xi3 -fp 217.3e3 -fz 12.5e3 -gain 1/(4.42e-9) -origin {940 70}
make ich_w_noise -name xi7 -i_val 100e-6 -i_variance 0 -origin {570 40}
make ich_w_noise -name xi8 -i_val 100e-6 -i_variance 0 -origin {570 160}
make name_net -name Sub -origin {840 70}
  make_wire 580 450 650 450
  make_wire 550 410 500 410
  make_wire 550 410 650 410
  make_wire 280 70 300 70
  make_wire 1450 70 1470 70
  make_wire 770 410 1420 410
  make_wire 1710 70 1630 70
  make_wire 1710 70 1720 70
  make_wire 1630 150 1720 150
  make_wire 1420 410 1460 410
  make_wire 1460 110 1460 410
  make_wire 580 300 1710 300
  make_wire 280 300 580 300
  make_wire 250 70 280 70
  make_wire 710 70 760 70
  make_wire 440 40 510 40
  make_wire 440 160 510 160
  make_wire 790 100 790 130
  make_wire 620 40 710 40
  make_wire 620 160 720 160
  make_wire 720 130 790 130
  make_wire 440 70 400 70
  make_wire 440 130 400 130
  make_wire 280 130 300 130
  make_wire 1710 70 1710 300
  make_wire 1460 110 1470 110
  make_wire 280 130 280 300
  make_wire 580 300 580 450
  make_wire 1100 70 1030 70
  make_wire 1290 70 1180 70
  make_wire 1370 70 1450 70
  make_wire 710 40 710 70
  make_wire 720 130 720 160
  make_wire 440 130 440 160
  make_wire 440 70 450 70
  make_wire 440 40 440 70
  make_wire 840 70 850 70
  make_wire 840 70 820 70
  make_text -origin {960 500} -text {Examples in CppSimView:}
  make_text -origin {990 540} -text {To observe dynamics:  select test.tr0}
  make_text -origin {990 570} -text {plotsig(x,'sd_in;vin')}
  make_text -origin {990 620} -text {To observe phase noise: select test_noise.tr0}
  make_text -origin {990 650} -text plot_pll_phasenoise(x,10e3,30e6,'noiseout')
  make_line 100 90 100 90
}

