module Shftreg(CLK, reset, load, data_in, shift, tdre_set, serial_out, data_out);
	input CLK, reset;
	input load;
	input [7:0] data_in;
	input shift;
	output reg tdre_set;
	output reg serial_out;
	reg [8:0] data_out;
	output [8:0] data_out;
	
always @ (posedge CLK or posedge reset)

	if (reset)
		begin	data_out <= 1;
				serial_out <=1;
				tdre_set <= 1;
		end
	else if (load)
		begin
				data_out <= {data_in, 1'b0};
				tdre_set <= 1;
		end
	else if (shift)
		begin
				serial_out <= data_out[0];
				data_out <= {1'b1, data_out[8:1]};
				tdre_set <= 0;
		end
	else
		begin
				data_out <= data_out;
				serial_out <= 1;
				tdre_set <= 0;
		end
		
endmodule
	
				
	