module clk_generator(clk50Mhz,clk_transmitter, clk_receiver );
	input clk50Mhz;
	output reg  clk_transmitter;
	output reg clk_receiver;
	reg [12:0] tp_reg, tn_reg;
	reg [9:0] rp_reg, rn_reg;
	
always  @ (posedge clk50Mhz)
	if (clk50Mhz) tp_reg <= tn_reg;
	else tp_reg <= tp_reg;


always  @ (tp_reg)
// next state logic	
	if (tp_reg == 5208) tn_reg =0;
	else tn_reg = tp_reg + 13'b0000000000001;
	


//output logic
always  @ (posedge clk50Mhz)
	if (tp_reg < 2604) clk_transmitter <= 0;
	else clk_transmitter <=1 ;

//----------------------------------------------

always  @ (posedge clk50Mhz)
	if (clk50Mhz) rp_reg <= rn_reg;
	else rp_reg <= rp_reg;
	
// next state logic	
always  @ (rp_reg)
	if (rp_reg == 651) rn_reg =0;
	else rn_reg = rp_reg + 10'b0000000001;

//output logic
always  @ (posedge clk50Mhz)
	if (rp_reg < 325) clk_receiver <= 0;
	else clk_receiver <=1 ;


endmodule
	