module Transmitter_CU(CLK, reset, byte_ready, t_byte, bit_count, load_shftreg, shift, clear, transCU_idle, ps);


	input CLK, reset;
	input byte_ready;
	input t_byte;
	input [3:0] bit_count;
	output load_shftreg;
	output shift;
	output clear;
	output reg transCU_idle;
	reg [1:0] ps, ns;
	
	reg [2:0] control;
	parameter [1:0] idle = 0, waiting = 1, sending = 2;
	
	//extra port for simulation
	output [1:0] ps;
	
always @ (posedge CLK or posedge reset)
	if (reset) ps <= idle;
	else ps <= ns;
	
always @ (ps or byte_ready or t_byte or bit_count)
begin
											 control = 3'b000;
	
	case (ps)
	idle:begin							
				transCU_idle = 1;				 control=3'b100;
									
				if (byte_ready)
					begin
								ns = waiting;control=3'b001;
					end
				else
						ns = idle;
		 end
//----------------------------------------------------------
	waiting:begin												                      
				transCU_idle=0;					control=3'b001;
										
				if (t_byte)
								ns=sending;
				else
								ns=waiting;
			end
//----------------------------------------------------------		
	sending: begin 
				transCU_idle=0;
									
				if (bit_count<10)
					begin
								ns=sending;	control= 3'b010;
					end
											
				else
					begin
						ns=idle;		control=3'b100;
					end 
			end
//----------------------------------------------------------					
	default: begin
				 transCU_idle=0;	ns=idle;	control=3'b100;
			 end						  
	endcase
end

assign clear = control[2];	
assign shift = control[1];
assign load_shftreg = control[0];

endmodule