module Bit_counter( CLK, reset, shift, bit_count, clr);
	input CLK, reset, shift, clr;
	output [count_width - 1:0]bit_count;
	reg [count_width - 1:0] bit_count;
	parameter count_width = 4;
	
	
always @ (posedge CLK or posedge reset)


	if (reset) bit_count<= 0;
	else if (shift) bit_count <= bit_count+4'b0001 ;
	else if (clr) bit_count <=0;
	else bit_count <= bit_count;

	
endmodule