module Transmitter_DPU(CLK, reset, data_in, load_datareg, tdre_set, tdre_clear, load_shftreg, shift, clear, bit_count, serial_out);

	input CLK, reset;
	input [7:0] data_in;
	input load_datareg;
	
	input load_shftreg;
	input shift;
	input clear;
	output tdre_set, tdre_clear;
	output [3:0] bit_count;
	output serial_out;
	wire [7:0] datareg_signal;
	
	
	Datareg		U_Datareg 
	(.CLK(CLK), .reset(reset), .data_in(data_in), .load_datareg(load_datareg), .tdre_clear(tdre_clear), .data_out(datareg_signal));
	
	
	Bit_counter	U_Bit_counter
	(.CLK(CLK), .reset(reset), .shift(shift), .bit_count(bit_count), .clr(clear));
	
	
	 Shftreg	U_Shftreg
	 (.CLK(CLK), .reset(reset), .load(load_shftreg), .data_in(datareg_signal), .shift(shift), .tdre_set(tdre_set), .serial_out(serial_out));
	 
endmodule