module Bit_counter1( CLK, reset, inc, count, clr);
	input CLK, reset, inc, clr;
	output [count_width - 1:0]count;
	reg [count_width - 1:0] count;
	parameter count_width = 4;
	
	
always @ (posedge CLK or posedge reset)
	if (reset) count<= 0;
	else if (inc) count <= count+ 4'b0001 ;
	else if (clr) count <=0;
	else count <= count;
	
endmodule
		
		