module Receiver_DPU ( CLK, reset,inc_sample, clr_sample, inc_bit, clr_bit, shift, load, sel_comp, serial_in, sample_eq, bit_eq, data_out);
	
	input CLK, reset;
	input inc_sample, clr_sample;
	input inc_bit, clr_bit;
	input shift;
	input load;
	input sel_comp;
	input serial_in;
	output reg sample_eq;
	output reg bit_eq;
	output [data_width-1:0] data_out;
	parameter data_width = 8;
	wire [3:0] sample;
	wire [3:0] bits;
	//wire [7:0] data;
	wire [7:0]  r_data;
	//extra port for simulation of receiver
	
	
//Rcv_datareg	U_Rcv_datareg
//(.CLK(CLK), .reset(reset), .load(load), .d(data), .q(data_out));

//Rcv_shftreg	U_Rcv_shftreg
//(.CLK(CLK), .reset(reset), .shift(shift), .d(serial_in), .q(data));

//for simulation of receiver
Rcv_datareg	U_Rcv_datareg
(.CLK(CLK), .reset(reset), .load(load), .d(r_data), .q(data_out));

Rcv_shftreg	U_Rcv_shftreg
(.CLK(CLK), .reset(reset), .shift(shift), .d(serial_in), .q(r_data));

Sample_counter	U_Sample_counter
(.CLK(CLK), .reset(reset), .inc(inc_sample), .count(sample), .clr(clr_sample));

Bit_counter1	U_Bit_counter1
(.CLK(CLK), .reset(reset), .inc(inc_bit), .count(bits), .clr(clr_bit));


always @ (sample or sel_comp)
	if 		(sel_comp ==0 && sample==4)	sample_eq = 1;
	else if (sel_comp ==1 && sample==7)	sample_eq = 1;
	else 								sample_eq = 0;
	
always @ (bits)
	if (bits == 9) bit_eq = 1;
	else 			bit_eq = 0;
	
endmodule