module UART_comm (clk50Mhz, reset_b, byte_ready, t_byte, load_datareg, data_in, serial_in, r_x_ready_in, tdre_set, tdre_clear, serial_out, transCU_idle, rdrf_set, rdrf_clear, error1, error2, data_output);

	input clk50Mhz, reset_b;
	input byte_ready, t_byte;
	input load_datareg;
	input [7:0] data_in;
	input serial_in;
	input r_x_ready_in;
	output tdre_set, tdre_clear;
	output serial_out;
	output transCU_idle;
	output rdrf_set, rdrf_clear;
	output error1, error2;
	output [0:7] data_output;
	wire reset;
	wire clk_transmitter, clk_receiver;
	
	
assign reset = ~reset_b;

clk_generator		U_Clock_generator
(.clk50Mhz(clk50Mhz), .clk_transmitter(clk_transmitter), .clk_receiver(clk_receiver));


UART_receiver		U_UART_Receiver
(.clk_receiver(clk_receiver), .reset(reset), .serial_in(serial_in), .r_x_ready_in(r_x_ready_in), .rdrf_set(rdrf_set), .rdrf_clear(rdrf_clear), .error1(error1), .error2(error2), .data_out(data_output) );


UART_transmitter	U_UART_Transmitter
(.clk_transmitter(clk_transmitter), .reset(reset), .byte_ready(byte_ready), .t_byte(t_byte), .load_datareg(load_datareg), .data_in(data_in), .tdre_clear(tdre_clear), .tdre_set(tdre_set), .serial_out(serial_out), .transCU_idle(transCU_idle));

endmodule















	
	