module UART_transmitter(clk_transmitter, reset, byte_ready, t_byte, load_datareg, data_in, tdre_clear,tdre_set, serial_out, transCU_idle);

	input clk_transmitter, reset;
	input byte_ready, t_byte;
	input load_datareg;
	input [7:0] data_in;
	output tdre_clear, tdre_set;
	output serial_out;
	output transCU_idle;
	//output sig_idle;
	wire load_shftreg, clear, shift;
	wire [3:0] bit_count;
	// extra port for simulation
	
	
	
Transmitter_DPU		U_Transmitter_DPU
(.CLK(clk_transmitter), .reset(reset), .data_in(data_in), .load_datareg(load_datareg), .tdre_set(tdre_set), .tdre_clear(tdre_clear), .load_shftreg(load_shftreg), .shift(shift), .clear(clear), .bit_count(bit_count), .serial_out(serial_out));	
	
	
Transmitter_CU		U_Transmitter_CU
(.CLK(clk_transmitter), .reset(reset), .byte_ready(byte_ready), .t_byte(t_byte), .bit_count(bit_count), .load_shftreg(load_shftreg), .shift(shift), .clear(clear), .transCU_idle(transCU_idle));	

endmodule
