module UART_receiver (clk_receiver, reset, serial_in, r_x_ready_in, rdrf_set, rdrf_clear, error1, error2, data_out);

	input clk_receiver, reset;
	input serial_in;
	input r_x_ready_in;
	output rdrf_set, rdrf_clear;
	output error1, error2;
	output [7:0] data_out;
	wire clr_sample, inc_sample, clr_bit, inc_bit;
	
	//wire shift, load, sel_comp, sam_eq_int,bit_eq_int;
	wire shift, load, sel_comp, sample_eq,bit_eq, r_shift;
	//// extra port fpr simulation of receive
	
	
	
//Receiver_DPU 	U_Receiver_DPU 
//(.CLK(clk_receiver), .reset(reset), .inc_sample(inc_sample), .clr_sample(clr_sample), .inc_bit(inc_bit), .clr_bit(clr_bit), .shift(shift), .load(load), .sel_comp(sel_comp), .serial_in(serial_in), .sample_eq(sam_eq_int), .bit_eq(bit_eq_int), .data_out(data_out), .sample(sample), .bits(bits), .r_data(r_data));

Receiver_DPU 	U_Receiver_DPU 
(.CLK(clk_receiver), .reset(reset), .inc_sample(inc_sample), .clr_sample(clr_sample), .inc_bit(inc_bit), .clr_bit(clr_bit), .shift(r_shift), .load(load), .sel_comp(sel_comp), .serial_in(serial_in), .sample_eq(sample_eq), .bit_eq(bit_eq), .data_out(data_out));

//Receiver_CU 	U_Receiver_CU
//(.CLK(clk_receiver), .reset(reset), .serial_in(serial_in), .r_x_ready_in(r_x_ready_in), .sample_eq(sam_eq_int), .bit_eq(bit_eq_int), .inc_sample(inc_sample), .clr_sample(clr_sample), .inc_bit(inc_bit), .clr_bit(clr_bit), .sel_comp(sel_comp), .shift(shift), .load(load),  .rdrf_set(rdrf_set), .rdrf_clear(rdrf_clear), .error1(error1), .error2(error2));

Receiver_CU 	U_Receiver_CU
(.CLK(clk_receiver), .reset(reset), .serial_in(serial_in), .r_x_ready_in(r_x_ready_in), .sample_eq(sample_eq), .bit_eq(bit_eq), .inc_sample(inc_sample), .clr_sample(clr_sample), .inc_bit(inc_bit), .clr_bit(clr_bit), .sel_comp(sel_comp), .shift(r_shift), .load(load),  .rdrf_set(rdrf_set), .rdrf_clear(rdrf_clear), .error1(error1), .error2(error2));

endmodule