module Rcv_shftreg (CLK, reset,shift, d, q);
	input CLK, reset, shift;
	input  d;
	output [width-1:0] q;
	reg [width-1:0] q;
	parameter width = 8;
	integer i;
	
always @(posedge CLK or posedge reset)
begin	
	if(reset) q<= 0;
	else if (shift)
		begin
			q[0] <= d;
				for (i=1; i<8; i=i+1)
					begin
						q[i] <= q[i-1];
					end
		end
	else q <= q;
end
	
endmodule