module Datareg (CLK, reset, data_in, load_datareg, tdre_clear, data_out);
	
	input CLK, reset;
	input [7:0] data_in;
	input load_datareg;
	output reg tdre_clear;
	output reg [7:0] data_out;
	
always @ (posedge CLK or posedge reset)
	if (reset) data_out <= 0;
	else if (load_datareg) 
			begin	
				data_out <= data_in;
				tdre_clear <= 1;
			end
	else 
			begin
				data_out <= data_out;
				tdre_clear <= 0;
			end

endmodule