module Receiver_CU (CLK, reset, serial_in,r_x_ready_in,sample_eq, bit_eq, inc_sample, clr_sample, inc_bit, clr_bit, sel_comp, shift, load, rdrf_set, rdrf_clear, error1, error2, ps);

	input CLK, reset;
	input serial_in;
	input r_x_ready_in;
	input sample_eq, bit_eq;
	output inc_sample, clr_sample;
	output inc_bit, clr_bit;
	output sel_comp, shift, load;
	output rdrf_set, rdrf_clear;
	output error1, error2;
	reg [2:0] ps, ns;
	output  [2:0] ps;
	reg error1, error2;
	reg rdrf_set, rdrf_clear;
	reg [6:0] control;
	parameter [2:0] s0=0, s1=1, s2=2, s3=3, s4 = 4;
	
always @ (negedge CLK or posedge reset)
	if (reset) 	ps <= s0;
	else		ps <= ns;
	
always @ (ps or sample_eq or bit_eq or r_x_ready_in or serial_in)
begin
	control = 7'b0101000;
	error1 = 0;
	error2 = 0;
	rdrf_set = 0;
	rdrf_clear = 1;
	
	case (ps)
		s0: begin 	control = 7'b0101000;
					error1 = 0;
					error2 = 0;
					rdrf_set = 0;
					rdrf_clear = 1;
			
				if (!serial_in) 		ns = s1;
				else					ns = s0;
			end
//----------------------------------------------------------------------------------
			
		s1: if (serial_in)		begin 	ns = s0;  control = 7'b0101000; end
			else 
				if(!sample_eq)	begin	ns = s1;  control = 7'b1001000; end
				else			begin	ns = s2;  control = 7'b0110000; end
//----------------------------------------------------------------------------------
				
		s2: 					begin	ns = s3;  control = 7'b0110000; end
	//control = 7'b0111000; end
//----------------------------------------------------------------------------------

		s3: if (!sample_eq)		begin	ns = s3;  control = 7'b1000100; end
			else
				begin
				  if (!bit_eq)	begin	ns = s3;  control = 7'b0110110; end
				  else 			begin 									error1 = 0; 
																		error2 = 0;
				
									  if (r_x_ready_in)	
										begin 
										ns = s0;  control = 7'b0101100; error1 = 1; 
										end
				
									  else if (!serial_in)
									    begin
										ns = s0;  control = 7'b0101100; error2 = 1;	
										end
									  else	
									    begin
									    ns = s4;  control = 7'b0101101;	
									    end	  
								 end
				end
		s4: begin 						ns = s0;  control = 7'b0101101; 
										rdrf_set =1; rdrf_clear = 0;
			end
	
//----------------------------------------------------------------------------------
   default: 							ns = s0;
	endcase 
end

assign inc_sample = control [6];	assign clr_sample = control [5];
assign inc_bit = control[4];		assign clr_bit = control[3];
assign sel_comp = control[2];		assign shift = control[1];
assign load = control[0];
					
endmodule