module Rcv_datareg (CLK, reset, load, d, q);
	input CLK, reset, load;
	input [0:7] d;
	output [0:7] q;
	reg [0:7] q;
	
always @(posedge CLK or posedge reset)
	
	if(reset) q<= 0;
	else if (load) q <= d;
	else q <= q;
	
endmodule