Title: testing verilog-A 

.hdl quantizer.va
.options post=1

VCLK	clk 	0		pulse 	0 1 1f 1f 1f 0.390625u 0.78125u
Vin 	in 		0 		SIN 	0 1 2k

Xquantizer1		out		in 		clk 	quantizer	levels=3 vh=1 vl=-1 vth =0 dir=1 td=0 tt=0
Rout	out		0		1meg

.option method=gear post=1
.options delmax=10n
.temp 25
.op
.tran 10n 20m

.end
