** Generated for: hspiceD
** Generated on: Feb 17 19:55:41 2009
** Design library name: beh_kundert
** Design cell name: PLL_usb_sim
** Design view name: schematic


.TRAN 1e-12 200e-6 START=0.0

.OP

.TEMP 25.0
.OPTION
*+    ARTIST=2
+    INGOLD=2
+    MEASOUT=1
+    PARHIER=LOCAL
*+    PSF=2

** Library name: beh_kundert
** Cell name: PLL_usb_sim
** View name: schematic
xi1 out in vco vmin=0 vmax=1 fmin=1.5e9 fmax=3e9 vl=0 vh=1.2 tt=100e-15 ttol=100e-15
*xi1 out in vco3_kundert *vmin=0 vmax=1 fmin=1.5e9 fmax=3e9 vl=0 vh=1.2 tt=100e-15 ttol=100e-15
v1 in 0 DC=1 *AC 1 PULSE 0 1.2 0 1e-9 1e-9 9e-9 20e-9
*i9 clk_fb div25_out divider1 vh=1.2 vl=0 vth=600e-3 ratio=2 dir=1 tt=1e-12 td=1e-12


.hdl "vco.va"

.END
