AMS Simulators - The Designer's Guide Community Forum

AMS Simulators - The Designer's Guide Community Forum https://designers-guide.org/forum/YaBB.pl?board=amssim AMS Simulators - The Designer's Guide Community Forum en-us The Designer's Guide Community Forum Tue, 15 Sep 2026 15:48:16 +0000 http://blogs.law.harvard.edu/tech/rss 30 how to solve the (SPECTRE-18):Segmentation fault https://designers-guide.org/forum/YaBB.pl?num=1766540742 The Designer's Guide Community Forum/AMS Simulators https://designers-guide.org/forum/YaBB.pl?num=1766540742 when the spectre fx run above 10h， the tools will display the following error log: Internal error found in spectre at time = 4.12725 ms during Transient Analysis `tran'.    FATAL (SPECTRE-18): Segmentation fault.        Encountered a critical error during simulation. Submit a Service Request via Cadence Online Support, including the netlist, the log files, the behavioral model files, and any other information that can help identify the problem        Encountered a critical error during simulation. Submit a Service Request via Cadence Online Support, including the netlist, the log files, the behavioral model files, and any other information that can help identify the problem ****ASSERTION STACK****        0x7954dac        0x9b297c        0x9b34b6        0x2b2810a96630        0x2b28133c9fc3        0x86591ad        0x86597c0        0x863c34d        0x862c094        0x85754f5        0x85755f9        0x857596f        0x857fba9        0x8582946        0x2b2810a8eea5        0x2b28133e096d ****LIBRARIES**** /edatools/cadence/spectre_test/spectre231/tools/spectre/bin/64bit/spectre [0x400000]        /lib64/libpthread.so.0 [0x2b2810a87000]        /lib64/libc.so.6 [0x2b28132e2000] Xcelium: How to insert different Interface Elements for different pins https://designers-guide.org/forum/YaBB.pl?num=1655905964 The Designer's Guide Community Forum/AMS Simulators https://designers-guide.org/forum/YaBB.pl?num=1655905964 I'm currently developing some Verilog-AMS models for analog circuits, in which I'm modelling analog signals using wreal types. So a typical module might look like the following: Code:<pre class="code" style="margin: 0px; width: 90%; overflow: auto;">module myblock ( vin, iout ); input vin; wreal vin; output iout; wreal iout; (...) endmodule </pre> I'm simulating these blocks both on top level, where all blocks are wreal models, and on block level, where this block will be used in a schematic view with Spectre components. In the latter case, I need to set up the interface elements correctly. The difficulty is that some pins operate in voltage mode while others operate in current mode. That means the interface elements need to have different settings in each case, mainly in the currentmode setting. In the Xcelium command-line flow, I could define something like this in my amscf.scs: Code:<pre class="code" style="margin: 0px; width: 90%; overflow: auto;">amsd { ie vsup=1.8 cellport="myblock.vin" currentmode=0 ie vsup=1.8 cellport="myblock.iout" currentmode=1 } </pre> In ADE, I would go to the Interface Element Setup window and select each pin to define the scope, then set the correct options. However, in each case I have to point specifically at each pin to tell the simulator what type of IE it needs. This is very cumbersome and error-prone in a large design where there might be dozens of pins. Is there a way to define something in the Verilog-AMS code that will tell the simulator what type of IE needs to be inserted? For example, to define pins as wreal_v and wreal_i? Or can I somehow tell the simulator to use different settings for pin names starting with "i"? how to set initial state of digital circuit in AMS simulation? https://designers-guide.org/forum/YaBB.pl?num=1637310434 The Designer's Guide Community Forum/AMS Simulators https://designers-guide.org/forum/YaBB.pl?num=1637310434 Do you have the DFF model, can you edit it to allow specification of an initial reg value? oscilalting convergence residue w/ veriloga signal generator https://designers-guide.org/forum/YaBB.pl?num=1563971305 The Designer's Guide Community Forum/AMS Simulators https://designers-guide.org/forum/YaBB.pl?num=1563971305 I was able to solve the problem by simplifying the layout used for extraction. Unfortunately I was not able to pinpoint anything in the design which has caused the issue. Many thanks for your help and explanations, Ken! Verilog AMS https://designers-guide.org/forum/YaBB.pl?num=1557553493 The Designer's Guide Community Forum/AMS Simulators https://designers-guide.org/forum/YaBB.pl?num=1557553493 I'm having difficulty understanding your circuit from the text; perhaps a schematic would help. In particular, is your OR gate connected to both inputs of the XOR? In which case, the XOR would never be true, since its inputs are both high or both low. I also am not familiar with ConnectRules18Vfullfast. Is 0.85V high enough to trigger? Floating node using spectre option https://designers-guide.org/forum/YaBB.pl?num=1532953895 The Designer's Guide Community Forum/AMS Simulators https://designers-guide.org/forum/YaBB.pl?num=1532953895 The topology checker naturally finds, reports, and fixes nodes without a DC path to ground, which includes floating nodes. Dangling nodes do not cause convergence issues as long as they have a DC path to ground. Dynamic floating nodes (generally caused by Verilog-A models) are not reported with a dedicated message. Instead, the simulation fails with a 'Singular Jacobian'. When it does, it generally reports the nodes or branches where the problem was found. This often leads you to the problematic node or branch. -Ken Faile Elaboration - ncelab: *E,CUCFUN https://designers-guide.org/forum/YaBB.pl?num=1557555127 The Designer's Guide Community Forum/AMS Simulators https://designers-guide.org/forum/YaBB.pl?num=1557555127 Hard to know without seeing more details, but did you supply the transistor model files to the simulator (in ADE this is under Setup->Model Libraries)? Support for AMS Simulation " Connect rule are not found in your AMS isntallation https://designers-guide.org/forum/YaBB.pl?num=1526359236 The Designer's Guide Community Forum/AMS Simulators https://designers-guide.org/forum/YaBB.pl?num=1526359236 Before wasting too much time, I wonder why you are using such an ancient version of the simulator? There have been many, many releases since then - there's no reason to be using something so old. Regards, Andrew. How to model strength using WREAL ? https://designers-guide.org/forum/YaBB.pl?num=1519966583 The Designer's Guide Community Forum/AMS Simulators https://designers-guide.org/forum/YaBB.pl?num=1519966583 Hi, I have tried strength modelling (strong1/strong0/weak1/weak0...) in Verilog-D. But, Can you suggest me, How to model strength using wreal in Verilog-AMS ? I have tried below model.... //////////////////////////////////////////////////////////////////////////////// assign (strong1 , strong0) #2 pad_int = ( pu_strng === 1'b0 && pd_strng === 1'b0 ) ? `VDDA : ( pu_strng === 1'b1 && pd_strng === 1'b1 ) ? `VSSA : ( pu_strng === 1'b0 && pd_strng === 1'b1 ) ? (`VDDA/2) : `wrealZState ; assign (weak1 , weak0) #5 pad_int = ( pu_weak === 1'b0 && pd_weak === 1'b0 ) ? `VDDA : ( pu_weak === 1'b1 && pd_weak === 1'b1 ) ? `VSSA : ( pu_weak === 1'b0 && pd_weak === 1'b1 ) ? (`VDDA/2) : `wrealZState ; /////////////////////////////////////////////////////////////////////////////// While simulation of above design, I am not getting any syntax error. But, not getting expected output. i.e. In case of pu_strng = 0 and pd_weak=1 ====> Output getting X In case of pd_strng = 1 and pu_weak=0 ====> Output getting X Thanks -Ravi Shekhda Simulation Accuracy of AMS simulation https://designers-guide.org/forum/YaBB.pl?num=1518212778 The Designer's Guide Community Forum/AMS Simulators https://designers-guide.org/forum/YaBB.pl?num=1518212778 Hello, I'm trying to simulate a 18-bit SAR ADC with both AMS and spectre + nclauch. In the simulation with AMS, some of the digital blocks are realized by using verilog and simulated together with the analog blocks. In the simulation with spectre + nclaunch, the output of the analog blocks from spectre simulation is stored and used in the pure digital simulation with nclaunch. Spectre + nclauch simulation shows a SNDR of about 16.3-bit while it is less then 10-bit in the ams simulation. I found that there were some errors in the comparator for the ams simulation as the CDAC settling to a small residual. I'm wondering if there is something missing in my ams simulation since people say spectre and ams provide the same accuracy. <a href="http://www.designers-guide.org/Forum/YaBB.pl?num=1492517241" target="_blank">http://www.designers-guide.org/Forum/YaBB.pl?num=1492517241</a> I generated a very simple simulation to see if there is any accuracy difference between them. Then I did see some, as shown in the attached file. Netlists in both cases are attached below. The inverter was realized in veriloga for spectre simulation and in verilog for ams simulation. ///////// spectre nestlist/////////////// simulator lang=spectre global 0 include "process_device_model.lib" section=tt V0 (net4 0) vsource type=pulse val0=0 val1=1.2 period=1u rise=1n fall=1n \ width=400.0n C2 (net07 0) capacitor c=1p C0 (net01 0) capacitor c=2.5p R1 (net3 net7) resistor r=1K R0 (net4 net01) resistor r=100K NM0 (net7 net01 0 0) n12ll w=1u l=60n nf=2 as=155f ad=95f ps=2.62u \ pd=1.38u nrs=95m nrd=95m sa=155n sb=155n sd=190n sca=0 scb=0 scc=0 \ m=1 V1 (net3 0) vsource dc=1.2 type=dc I5 (net07 net010) inv0 td=2e-10 tt=2e-10 E0 (net010 0 net7 0) vcvs gain=1.0 simulatorOptions options reltol=1e-3 vabstol=1e-6 iabstol=1e-12 temp=30.0 \ tnom=27 scalem=1.0 scale=0.9 gmin=1e-12 rforce=1 maxnotes=5 maxwarns=5 \ digits=5 cols=80 pivrel=1e-3 sensfile="../psf/sens.output" \ checklimitdest=psf tran tran stop=3u errpreset=conservative step=1n write="spectre.ic" \ writefinal="spectre.fc" annotate=status maxiters=5 finalTimeOP info what=oppoint where=rawfile modelParameter info what=models where=rawfile element info what=inst where=rawfile outputParameter info what=output where=rawfile designParamVals info what=parameters where=rawfile primitives info what=primitives where=rawfile subckts info what=subckts where=rawfile saveOptions options save=allpub ahdl_include "./test/inv0/veriloga/veriloga.va" ////////////// ams netlist/////////////// `include "disciplines.vams" `include "userDisciplines.vams" `timescale 1ns / 1ns (* cds_ams_schematic *) module amstest1 (); vsource #(.type("pulse"), .val0(0), .val1(1.2), .period(1u), .rise(1n), .fall(1n), .width(400.0n)) V0 (net4, cds_globals.\gnd! ); capacitor #(.c(1p)) C2 (net07, cds_globals.\gnd! ); capacitor #(.c(2.5p)) C0 (net01, cds_globals.\gnd! ); resistor #(.r(1K)) R1 (net3, net7); resistor #(.r(100K)) R0 (net4, net01); n12ll #(.w(1u), .l(60n), .nf(2), .as(155f), .ad(95f), .ps(2.62u), .pd(1.38u), .nrs(95m), .nrd(95m), .sa(155n), .sb(155n), .sd(190n) , .sca(0), .scb(0), .scc(0), .m(1)) (* integer passed_mfactor = "m"; *) NM0 (net7, net01, cds_globals.\gnd! , cds_globals.\gnd! ); vsource #(.dc(1.2), .type("dc")) V1 (net3, cds_globals.\gnd! ); inv0 I5 ( .out(net07), .in(net010)); vcvs #(.gain(1.0)) E0 (net010, cds_globals.\gnd! , net7, cds_globals.\gnd! ); endmodule `include "disciplines.vams" `include "userDisciplines.vams" module cds_globals; // Global Signals electrical \gnd! ; ground \gnd! ; // Design Variables endmodule // This is the Cadence AMS Designer(R) analog simulation control file. // It specifies the options and analyses for the Spectre analog solver. simulator lang=spectre global 0 simulatorOptions options temp=30.0 tnom=27 scale=0.9 scalem=1.0 \ reltol=1e-3 vabstol=1e-6 iabstol=1e-12 gmin=1e-12 rforce=1 maxnotes=5 \ maxwarns=5 digits=5 pivrel=1e-3 checklimitdest=psf tran tran stop=3u errpreset=conservative step=1n write="spectre.ic" \ writefinal="spectre.fc" annotate=status maxiters=5 finalTimeOP info what=oppoint where=rawfile modelParameter info what=models where=rawfile element info what=inst where=rawfile outputParameter info what=output where=rawfile wave_out options rawfmt=sst2 amsd{ ie vsup=1.2 discipline=logic } # This is the NC-SIM(R) probe command file # used in the AMS-ADE integration. # # Database settings # if { [info exists ::env(AMS_RESULTS_DIR) ] } { set AMS_RESULTS_DIR $env(AMS_RESULTS_DIR)} else {set AMS_RESULTS_DIR "../psf"} database -open ams_database -into ${AMS_RESULTS_DIR} -default # # Probe settings # probe -create -emptyok -database ams_database {amstest1.net4} probe -create -emptyok -database ams_database {amstest1.net7} probe -create -emptyok -database ams_database {amstest1.net07} probe -create -emptyok -database ams_database {amstest1.net01} Could anyone tell me what I missed in my simulation? Thanks, Quan