10 most recent topics - The Designer's Guide Community Forum

10 most recent topics - The Designer's Guide Community Forum https://designers-guide.org/forum/YaBB.pl?catselect=modeling - The Designer's Guide Community Forum en-us The Designer's Guide Community Forum Sat, 10 Oct 2026 19:24:30 +0000 http://blogs.law.harvard.edu/tech/rss 30 Semiconductor Devices - Why use macros to define Verliog-A model/instance parameters? https://designers-guide.org/forum/YaBB.pl?num=1719436097/1#1 The Designer's Guide Community Forum/Semiconductor Devices https://designers-guide.org/forum/YaBB.pl?num=1719436097/1#1 I don't know, but if I were to guess, it is due to limitations in the various simulators they are supporting. By using defines, they can keep their standard definition of the model constant for all simulators, with the adaptation of the model to particular simulators using simulator specific defines. Passive Devices - How to reduce substrate coupling to the high frequency clock routing https://designers-guide.org/forum/YaBB.pl?num=1678927667/0#0 The Designer's Guide Community Forum/Passive Devices https://designers-guide.org/forum/YaBB.pl?num=1678927667/0#0 Hi, I am using one of the top metals (for the sake of discussion let's call it m5) in the given technology to ship a high frequency complementary (differential) clock from one point to the destination (by high frequency I meant +50GHz). Let's say I have 100-200um differential traces (m5) and side-shielded by the same metal (m5). Do you think putting lower metals (let's say m2) as a ground plane underneath of the clock path and connect it to a substrate via a substrate contact would reduce the substrate coupling? how does it reduce the coupling? how to model that ? which tools can model the substrate coupling/noise ? Thanks   Behavioral Models - Clamping Function https://designers-guide.org/forum/YaBB.pl?num=1676993139/2#2 The Designer's Guide Community Forum/Behavioral Models https://designers-guide.org/forum/YaBB.pl?num=1676993139/2#2 In a function format for use with "real" datatypes: Code:<pre class="code" style="margin: 0px; width: 90%; overflow: auto;">analog function real soft_limit; input in; real in; input lim_pos,lim_neg,soft; real lim_pos,lim_neg,soft; // Soft should be from 0 to 0.5 real band = (lim_pos-lim_neg)*soft, vlow_1 = lim_neg+band, vhigh_1 = lim_pos-band; begin if (in>vhigh_1) soft_limit = vhigh_1+band*(1.0-exp(-(in-vhigh_1)/band)); else if (in<vlow_1) soft_limit = vlow_1 -band*(1.0-exp( (in-vlow_1 )/band)) ; else soft_limit = in ; end endfunction </pre> Passive Devices - Ideal Directional coupler in Cadence https://designers-guide.org/forum/YaBB.pl?num=1676554899/1#1 The Designer's Guide Community Forum/Passive Devices https://designers-guide.org/forum/YaBB.pl?num=1676554899/1#1 Dear Kyle, > I need an ideal passive I/Q generation network in circuit for phase shifter > simulation. > Does anyone knows how can I build one in virtuoso (cadence)? There is a behavioral quadrature generator in the rfLibrary called "quadrature" than can generate I and Q phased clocks from its "lead" and "lag" outputs. There is also a phase shifter called "shifter" that accepts an input and generates signals in quadrature that models an RC based phase splitter. As such, its quadrature output amplitudes vary with frequency. > Is there any behavior model of directional coupler in analoglib? No. You might be able to build one with components in the analogLib, but to my knowledge, there is not a specific behavioral model for a directional coupler in analogLib. Shawn Transmission Lines and Other Distributed Devices - EM simulation with high resistivity substrate in CMOS IC technology https://designers-guide.org/forum/YaBB.pl?num=1675569363/0#0 The Designer's Guide Community Forum/Transmission Lines and Other Distributed Devices https://designers-guide.org/forum/YaBB.pl?num=1675569363/0#0 Hi, Is there a way to account for high resistivity substrate in EM simulation software? I am designing an inductor in a CMOS process and using high resistivity substrate to get high Q factor. I have momentum and emx software. Semiconductor Devices - Modelling MOS gate cap variation with VGS voltage in transient https://designers-guide.org/forum/YaBB.pl?num=1645781509/1#1 The Designer's Guide Community Forum/Semiconductor Devices https://designers-guide.org/forum/YaBB.pl?num=1645781509/1#1 Your understanding is not correct. Carriers in the inversion layer come not form the the substrate (as minority carriers), but from source / drain easily doped regions, which is as very fast process - of the order of transit time, probably ps range (of course, depends on gate lengths etc.). But another questions is - are you doing SPICE simulations? If so, your results depend on what's included into the SPICE model. I think she "non-quasi-static" effects are included in the latest SPICE models, but I am not sure how accurate those models are, and - whether that result matters for you or not. Passive Devices - Dielectric Absorption https://designers-guide.org/forum/YaBB.pl?num=1641541379/4#4 The Designer's Guide Community Forum/Passive Devices https://designers-guide.org/forum/YaBB.pl?num=1641541379/4#4 I would not exclude semiconductor device related effects - I observed various tricky time-dependent effects in photodetectors and photodiodes. Especially if you have floating nets, floating wells, etc. - lifetime in semiconductors can be large, seconds or longer (depending on temperature). Behavioral Models - Minor glitches in nonlinear magnetics paper https://designers-guide.org/forum/YaBB.pl?num=1505832899/10#10 The Designer's Guide Community Forum/Behavioral Models https://designers-guide.org/forum/YaBB.pl?num=1505832899/10#10 There's a nice demo at Wolfram: <a href="http://demonstrations.wolfram.com/JilesAthertonModelOfMagneticHysteresis/" target="_blank">http://demonstrations.wolfram.com/JilesAthertonModelOfMagneticHysteresis/</a> which includes units for the Jiles-Atherton parameters: ms in A/m a in A/m k in A/m c and alpha are dimensionless Behavioral Models - Summarized phrasing of below topic "Outp.ref kT/C noise combined with an in https://designers-guide.org/forum/YaBB.pl?num=1636713101/14#14 The Designer's Guide Community Forum/Behavioral Models https://designers-guide.org/forum/YaBB.pl?num=1636713101/14#14 Fig31 - ZOH or SandH Stand-alone Bode-plot ScrSh02.png Behavioral Models - Output-referred kT/C noise combined with T&H and with sw.cap integrator https://designers-guide.org/forum/YaBB.pl?num=1636017073/0#0 The Designer's Guide Community Forum/Behavioral Models https://designers-guide.org/forum/YaBB.pl?num=1636017073/0#0 Output-referred kT/C noise combined with T&H and with sw.cap integrator Best is to read the attached .pdf, but here a very brief summary: *) For kT/C noise combined with a Track And Hold, equations provided by Ken Kundert (thanks a lot!) for the T&H fit perfectly to Cadence sim. results. (Adding his "Ideal S&H” makes no difference here.) *) However, if I add a switched-capacitor integrator, NOW SUDDENLY I HAVE TO TAKE THE EQUATION FOR A SAMPLE & HOLD (S&H) to fit the Cadence sim. result (at least up to fs/2). Adding his "Ideal S&H” in this case does make a difference. => What is from the concept point of view the correct procedure / flow diagram for obtaining the correct discrete-time total integrator output-referred kT/Cs noise and why? Example: Generate kT/C noise ==> Process it with the T&H and/or S&H (??) ==> Multiply by integrator transfer function ==> Do sampling (again)?! Up to my knowledge, it seems, no one has conceptually described this in an understandable way up to now. As said, I would be VERY happy if one could bring some light into this topic! Many 1000 thanks in advance and best regards, Bernd (Reference = Paper used: "Simulating Switched-Capacitor Filters with SpectreRF - Ken Kundert")