https://designers-guide.org/forum/YaBB.pl?catselect=verif - The Designer's Guide Community Forum en-us The Designer's Guide Community Forum Tue, 15 Sep 2026 17:09:24 +0000 http://blogs.law.harvard.edu/tech/rss 30 https://designers-guide.org/forum/YaBB.pl?num=1760428915/3#3 The Designer's Guide Community Forum/Analog Functional Verification https://designers-guide.org/forum/YaBB.pl?num=1760428915/3#3 <b>Quote:</b><br /><div class="quote" style="width: 90%; overflow: auto;">3. For analog circuits in general, how do we build a complete verification flow? And more practically, how can we prove that a designed analog circuit is truly qualified? This is another key confusion I haven’t been able to resolve. </div><br />Fundamentally a complete verification flow includes both performance and functional verification.  Knowing how much to do is something that comes from experience.  Of course you should verify all required specs and all required functionality.  This later requirement means that you must exercise all modes and settings.  Most analog circuits these days do not contain significant state (digital state machines), so functional verification largely requires exercising all digital wires that connect to the circuit.<br /> https://designers-guide.org/forum/YaBB.pl?num=1748102444/1#1 The Designer's Guide Community Forum/Analog Performance Verification https://designers-guide.org/forum/YaBB.pl?num=1748102444/1#1 hi，all！<br />To analyze the pole-zero effects, I also attempted to perform a PZ simulation (Pole-Zero analysis), the results of which are attached. https://designers-guide.org/forum/YaBB.pl?num=1718108527/1#1 The Designer's Guide Community Forum/Analog Functional Verification https://designers-guide.org/forum/YaBB.pl?num=1718108527/1#1 Hey, I am sorry for the confusion, but while writing this post I realized my own mistake in calculating the period and setting up the transient simulation.<br />I made a mistake with the analysis tran time.<br />It is working as it should, it is making 1000 points in 6.67us (MICRO seconds) and I was simulating in 6.67ns, so of course no results to show there...<br />and I counted the zeros wrongly...<br /><br /><br />Anyway, I searched for a way to delete my post and haven't found it yet, but if pointed I can delete it. https://designers-guide.org/forum/YaBB.pl?num=1701422800/15#15 The Designer's Guide Community Forum/Analog Performance Verification https://designers-guide.org/forum/YaBB.pl?num=1701422800/15#15 The image posted here is a representation of the analysis and in a real bench, its a single source of each type and both DC and AC are part of the same. XF is interesting option.<br /><br />Can common mode gain be measured with this configuration, or is a different setup required? https://designers-guide.org/forum/YaBB.pl?num=1696579849/1#1 The Designer's Guide Community Forum/Analog Functional Verification https://designers-guide.org/forum/YaBB.pl?num=1696579849/1#1 Take a look at <a href="https://designers-guide.org/verilog-ams/functional-blocks/data-converter/converter-lrm.vams" target="_blank">https://designers-guide.org/verilog-ams/functional-blocks/data-converter/converter-lrm.vams</a><br /><br />However, be aware that you cannot use such a model in a Cadence schematic. &nbsp;Schematics do not allow the number of lines in a wire to be variable. https://designers-guide.org/forum/YaBB.pl?num=1694181814/3#3 The Designer's Guide Community Forum/Analog Functional Verification https://designers-guide.org/forum/YaBB.pl?num=1694181814/3#3 You might try reading a few bytes from /dev/random or /dev/urandom and using that as the initial seed.<br /><br />You definitely need a transition function around *rnd* in your contribution statement. https://designers-guide.org/forum/YaBB.pl?num=1691027150/7#7 The Designer's Guide Community Forum/Analog Functional Verification https://designers-guide.org/forum/YaBB.pl?num=1691027150/7#7 Verilog-AMS is a good skill to have. &nbsp;And the ability to write testbenches in Verilog-AMS is a particularly useful aspect of that. &nbsp;I suggest that you think of learning and using Verilog-AMS as an investment.<br /><br />You can write testbenches in Verilog-A but it is ugly and nobody that knows Verilog-AMS would do so. &nbsp;Since it is unpopular, I cannot point you to any examples that you could learn from. &nbsp;There are some things on functional modeling in Verilog-AMS, which is helpful but not the whole story (<a href="https://verilogams.com/tutorials/index.html" target="_blank">Functional modeling in Verilog-A</a>). https://designers-guide.org/forum/YaBB.pl?num=1679692689/2#2 The Designer's Guide Community Forum/Analog Functional Verification https://designers-guide.org/forum/YaBB.pl?num=1679692689/2#2 Hi Ken,<br />Thank you very much for the detailed explanation. <br /><br />My apologies, it was a typo on my part what I meant to say was that I set the <b> `timescale to 1s/1ps </b>from the command line.<br /><br />The ADE L simulation had the timescale set to 1ns/1ns which perfectly fits the situation you explained.<br /><br />Kind Regards,<br />Zaidi https://designers-guide.org/forum/YaBB.pl?num=1661841365/5#5 The Designer's Guide Community Forum/Analog Functional Verification https://designers-guide.org/forum/YaBB.pl?num=1661841365/5#5 If you want help with a specific model, you should show the model. &nbsp;I cannot see what you are doing wrong unless I can see the code. https://designers-guide.org/forum/YaBB.pl?num=1655257724/1#1 The Designer's Guide Community Forum/Analog Performance Verification https://designers-guide.org/forum/YaBB.pl?num=1655257724/1#1 I'm not exactly sure what you mean by &quot;simulating start up failure&quot;. &nbsp;Presumably you are trying to give it a good kick to get it started and see if it can sustain the oscillation?<br /><br />I have see people use three ways to start an oscillator:<br />1. using initial conditions<br />2. using a tickler source<br />3. using transient noise<br /><br />Using transient noise is the least reliable and least efficient. &nbsp;Using initial conditions tends to work very well for ring oscillators. &nbsp;Using a tickler source tends to work less well because people often put the source on the supply, and the mode of oscillation is not very sensitive to perturbations on the supply. &nbsp;This is particularly true for differential ring oscillators.<br /><br />If the oscillation does not sustain, it still might not be an issue with the circuit. &nbsp;Simulators can exhibit numerical damping. &nbsp;To reduce the chance that the simulator quenches the oscillation due to numerical damping, set maximum time step to get at least 30 time points per cycle and switch the integration method to trapezoidal rule.<br /><br />-Ken