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Design >> RF Design >> Integer Boundary Spurs for Frac N Synthesizer
https://designers-guide.org/forum/YaBB.pl?num=1178144443

Message started by rf_ee on May 2^nd, 2007, 3:20pm

Title: Integer Boundary Spurs for Frac N Synthesizer
Post by rf_ee on May 2^nd, 2007, 3:20pm

What are the methods for reducing the integer boundary spurs in a Frac N synthesizer?

(Spurs occuring when the fractional value is quite low)

The loop bandwidth cannot be changed due to settling time requirements.

The synthesizer architecture can be modified.

It is preferred not to change the reference frequency.

Any information on this topic would be appreciated.

Thanks!

Title: Re: Integer Boundary Spurs for Frac N Synthesizer
Post by DaveB on May 2^nd, 2007, 5:29pm

Can you change the Sigma Delta modulator to add LSB dithering? You may not be able to do much about it.

Dave

Title: How can I simulate jitter in hspice or spectre
Post by hamen on May 3^rd, 2007, 11:23am

Dear
I am a master student in KULeuven. I used your method for modelling of
noise in pll as a jitter. I want to simulate the jitter in hspice or
spectre. In the other words, how can I simulate the jitter and see the
power density of noise in the output of the close loop pll using spectre
or hspice.

thanks in advance

Mohammad Masoumi