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Design >> RF Design >> Deep N-well layout
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Message started by sandman on Jun 5^th, 2007, 12:45pm

Title: Deep N-well layout
Post by sandman on Jun 5^th, 2007, 12:45pm

Hi,

Would anyone know how the deep n-well is connected in the layout for capacitors and MOSFETs ? Does it have to be connected to any of the supplies Vdd/Gnd ? Is it tied to the bulk ? Is it left floating ? During a DRC, I end up with a psubStampError and have a feeling it is because I've left the deep N-well floating.

I'm designing this for an RF IC.

Any help is appreciated. Thanks, in advance. Cheers.

Title: Re: Deep N-well layout
Post by ACWWong on Jun 5^th, 2007, 2:09pm

It should be connected as depicted in the schematic. Most FETs or MOScaps modern design kits will either have an explicit connection for the deep N-well, or an inherited net.

If its not part of the schematic, its better to tie to VDD. That way the Nwell to psub diode is at maximum reverse bias and so minimum capacitance.

Title: Re: Deep N-well layout
Post by sandman on Jun 6^th, 2007, 4:35am

Thanks for that, ACWWong

I am using the TSMC 0.18. The schematic doesn't seem to show any explicit connections for the d-nwell. I was of the same opinion (that I should connect it to VDD to minimise the diode cap.), but was wondering that it would complicate the layout with the additional connection to VDD. That would make an already compact layout pretty crowded !
Have you had a similar experience with TSMC 0.18, D-Nwell ?

Title: Re: Deep N-well layout
Post by krishnap on Jun 6^th, 2007, 7:13am

Typically Nwell of dNwell device would be connected to VDD.
Also there would be DRC rule for spacing between Deep nwells, which
will make the area larger, compared to using normal devices.

Regards,
Krishna

Title: Re: Deep N-well layout
Post by sandman on Jun 8^th, 2007, 6:37am

Thanks for all your replies !