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https://designers-guide.org/forum/YaBB.pl Design >> Mixed-Signal Design >> constant reference loading MDAC https://designers-guide.org/forum/YaBB.pl?num=1188483036 Message started by vivkr on Aug 30th, 2007, 7:10am |
Title: constant reference loading MDAC Post by vivkr on Aug 30th, 2007, 7:10am Hi, I am looking for a constant reference loading MDAC structure because of problems with the conventional 1.5-bit MDAC (Please see attached PS). I am assuming a fully differential arrangement. If you look carefully, the amplification phase involves connecting the bottom-plate of CS to either +/- VREF or AGND (Common mode reference). This implies that the load seen by the reference is code-dependent. This can be fixed with dummy cap banks. The more serious problem is that this is a 3-point DAC, which is not guaranteed to be inherently linear. Any offset on the differential reference levels +/- VREF will show up as DNL. I considered use of a scheme similar to the one given in the TCAS-II (May 2004 paper) by Yoo, Park, Moon where CS would be split into 2 halves CS1 and CS2. Now, for +/-VREF, one could connect both halves to either reference, while for providing 0V DAC voltage, you would now connect CS1 to +VREF and CS2 to -VREF. Thus, only a 2-point DAC is used which is fundamentally linear. http://web.engr.oregonstate.edu/~moon/research/files/cas2_may_04.pdf However, this scheme is not symmetric and will result in increased distortion for very small inputs close to zero. This is often a requirement. Can anyone suggest a scheme which would avoid the problem of having to use a 3-point DAC but which would give good linearity at low signal levels? Thanks Vivek |
Title: Re: constant reference loading MDAC Post by vivkr on Sep 4th, 2007, 5:20am Hi, Looks like the topic interested nobody. Perhaps I should have not forgotten to add "pipelined ADC" in the title. Anyway, I did not find any convincing solution for this problem, although I saw some people who use 2 separate capacitors, one for feeding the input, and one for feeding the DAC feedback. The idea is to increase the number of caps connected from +VREF/-VREF to the summing node as the DAC code increases. This way, nothing is connected at all to realize 0 DAC feedback. However, it is not obvious whether this method does not have a hidden trap which causes the same problems as I mentioned. It will also have the additional burden of varying feedback factors for the opamp and slightly nonoptimal compensation as a result. It will also have more noise in general as more caps are connected to the OTA although the net input charge is the same. Regards Vivek |
Title: Re: constant reference loading MDAC Post by ywguo on Sep 8th, 2007, 8:04pm Hi Vivek, Sure I am interested in your topic. :) Quote:
Here I have one question. Normaly I short the bottom-plate of CS if the code decide to connect to AGND. So I don't think that an offset on the differential reference levels +/- VREF will show up as DNL. Am I right? Best regards, Yawei |
Title: Re: constant reference loading MDAC Post by vivkr on Sep 17th, 2007, 2:40am Hi Yawei, Won't it? I was thinking about it but maybe I thought too much and got it all wrong. If you look at the 1.5b MDAC (say). Now, in the middle segment, Vo = 2*Vin, you connect the bottom plate of CS to AGND. In the top segment to +VR, in the bottom segment to -VR. If the differential voltages +/-VR have an offset to AGND of voff, then the step transition going from the middle region to the side will be changed by this. Normally, you should have a step height of +VR in each case (assuming +/-VR reference). But it will be now VR +/- voff. This change is equivalent to having some DNL in there, isn't it? Regards Vivek |
Title: Re: constant reference loading MDAC Post by vivkr on Sep 17th, 2007, 4:09am Hi Yawei, If you think that the MDAC is always trying to realize Vout = 2*Vin - Vdac, then you can see the problem. Normally, Vdac should take values { -VR, 0, +VR } . This is a linear 3-point DAC, but if there is an offset voff on AGND, then you realize { -VR, voff, +VR }. This is now a nonlinear 3-point DAC, and there seems no way of fixing it in this form. What do you say? Regards Vivek |
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