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Design >> Analog Design >> Is this a good way to place dummy transistors ?
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Message started by DoYouLinux on Sep 27^th, 2007, 1:57am

Title: Is this a good way to place dummy transistors ?
Post by DoYouLinux on Sep 27^th, 2007, 1:57am

Hi all,

I am designing a 7 GHz ring oscillator and looking for a good practical way to place dummy transistors for each functional transistor.

As shown in the attached figure, for example, in case that I have a functional transistor having a size of 10/0.18 (5/0.18 with 2 fingers) and I would like to add dummy transistors to this functional transistor. Is it correct that I just add two independent (isolated) transistors, each having a size of 5/0.18 and all terminals are grounded (for NMOS) to both sides of the functional transistor ? Then, as shown in the layout, the distance between the dummy transistors and the functional transistors have to kept as small as possible, right ?

Thank you very much in advance,

DYLinux

Title: Re: Is this a good way to place dummy transistors
Post by Stefan on Sep 27^th, 2007, 2:06am

Two kind of thins must be thought of :
1) matching hardware to model
2) matching hardware to hardware

The first one depends on the process and design kit you're using. For a single fingered transistor you're idea would be correct. Check with your Design Kit manual to find out (if possible) how your transistor was characterized.

The second one might be of more importance when designing a ring oscillator.
Each stage should match perfectly to each other, while occupying as small area as possible (otherwise you'd typically prefer an LC-Osc).
I'd therefore recommend to not use single transistors as dummys, but to share source/drain between dummy transistor and active transistor.
That would mean that you just add another "channel/gate/source" combination to either side of your active transistor.

Title: Re: Is this a good way to place dummy transistors
Post by Berti on Sep 27^th, 2007, 7:05am

Dear Stefan,

in general I agree with you. But be aware of multifinger layout when using 130nm and below, where mechanical stress due to STI becomes
an issue (the threshold voltage will depend on the distance between the poly gate and the STI).
It is therefore recommend to use a single transistor for each device for good matching.

Regards

Title: Re: Is this a good way to place dummy transistors
Post by DoYouLinux on Sep 27^th, 2007, 12:16pm

Thank you very much Stefan and Berti ;)

What I am still wondering is that:

1) In case that I connect the dummy transistors to each side of a functional transistor (sharing the source/drain region), what about the gate ? Is it necessary to connect the gate of the dummy to the gate of the functional transistor ? Or can I just ground the gate (for NMOS) to deactivate the dummy ?

2) Since my design is working at very high frequency, so if possible, I do not want to attach the dummy transistors to the functional transistor (trying to avoid further loading the functional transistor with more parasitic capacitance). Due to this concern, can I still place the dummy transistors separately from the function transistor and ground all terminals as shown in the figure ? To avoid the edge effect, I agree that sharing the drain/source region would be better, but concerning the contribution of capacitance from the dummy devices, would it also be possible to use separate dummy devices to avoid this contribution ?

Thank you very much to you all again :)

DYLinux

Title: Re: Is this a good way to place dummy transistors
Post by tosei on Sep 27^th, 2007, 12:43pm

Hi Stefan,

I would ground the gate so that there is no change for any leakage current to flow through the dummies. In addition, avoiding such gate from being connected to the active transistor gate would help you reduce parasitic capacitances, which I bet are critical considering the speed you are working at.
Same idea for drain/source contacts. I would not tie them together.

Hope this helps

tosei

Title: Re: Is this a good way to place dummy transistors
Post by RobG on Sep 28^th, 2007, 12:38pm

I may be missing something, but I think you would be better off sharing drains of the dummies with the "functional" transitor. This is easy to do since they are connected to ground. In other words, use a single diffusion with four gate stripes and five sets of contacts.

I'm not sure what this will buy you, however, since you only have one "functinoal" transistor. Ideally, all the matched transistors should be within the same group of dummies.

Title: Re: Is this a good way to place dummy transistors
Post by carlgrace on Oct 2^nd, 2007, 10:15am

Berti,

Considering the STI stress, using a single fingered device will not give best matching, in fact all it will do is subject the device to the maximum stress condition. To remove STI stress you need enough dummies such that each finger sees a similar distance to the oxide definition (OD) edge. For 90nm for example, it is about 3 um, so you would need enough dummies so each finger is more than 3 um from the OD edge... in this case you would get minimum stress.

Carl

Title: Re: Is this a good way to place dummy transistors
Post by Stefan on Oct 3^rd, 2007, 3:05am

Although (if supported by your design kit) the easiest way would be to use standard-cell single transistors which are readily characterized using guard ring and everything... you wouldn't need to care about placing dummies then, although you might have to use some more space ...

Title: Re: Is this a good way to place dummy transistors
Post by Berti on Oct 3^rd, 2007, 4:58am

Hi Carl and Stefan,

of course, placing dummies next to every device or using a kind of standard-cell single transistor would eliminate the
stress issue. But are you guys really doing this in your layouts?
I guess the layout would become much larger .. and parasitics, too.

Title: Re: Is this a good way to place dummy transistors
Post by RobG on Oct 3^rd, 2007, 8:38am

carlgrace wrote on Oct 2^nd, 2007, 10:15am:

Carl - I've never worked with STI (shallow trench isolation)... how did you arrive at 3um? And, for the scenario you mention, would the STI "ring" around the transistors be the OD that you refer to?

Title: Re: Is this a good way to place dummy transistors
Post by carlgrace on Oct 3^rd, 2007, 12:25pm

Berti,

Yes I am doing this in 65 nm analog design. It is a must... not only does it help with stress, it also helps with brutal poly fill requirements. The parasitics aren't much really if you are careful.

Carl

Title: Re: Is this a good way to place dummy transistors
Post by carlgrace on Oct 3^rd, 2007, 12:27pm

Rob G,

I came to the 3um number by simulating Vt and Iref shift in devices with varying amounts of dummies until the vt converged. If you can handle more mismatch, you can handle smaller distance to the OD edge.

yes, OD is the edge of the oxide definition... this is where the STI is applied.

Carl

Title: Re: Is this a good way to place dummy transistors
Post by Stefan on Oct 4^th, 2007, 12:11am

@Berti : That really depends on the application you're targeting. if you want to be able to (nearly) accurately predict the oscillating frequency (without demands for highest frequency), the use of standard cells is quite common. Yes, interconnects do give you more parasitics then, but depending on transistor size, they're still negligible.

Title: Re: Is this a good way to place dummy transistors
Post by Berti on Oct 4^th, 2007, 12:58am

Hi Stefan, when talking of oscillation frequency you assume an oscillator design?
... and what's about post-layout simulation taking into account the vth-shift?

and Carl, using single devices and making sure that the distance from poly
to the OD-edge is the same for every device, also the influence of stress should
be the same for each device. And devices would still match.?...

Thank you for explanations.

Regards

Title: Re: Is this a good way to place dummy transistors
Post by carlgrace on Oct 4^th, 2007, 10:23am

Berti,

You are correct. However, to do this you cannot share source/drain or use multi finger device, so you may have additional parasitics in some cases that are not worth the trade off. In this case the devices would be in their own little OD islands... it may solve STI issue, but with lower packing density it would be hard to meet poly fill requirement without adding dummy poly. In that case, you may as well add the dummy devices and save the cost and area!

Carl

Title: Re: Is this a good way to place dummy transistors
Post by loose-electron on Oct 5^th, 2007, 4:29pm

A 7 GHz ring oscillator?

Instead of obsessing on matching, why dont you AC couple each stage so that matching offset is a non issue? Need to have a startup circuti on the ring, but thats ok.

Or, if you are only coming off one stage of the ring, then matching is a non-issue -

At 7GHz you want minimal parasitics.
Jerry

Title: Re: Is this a good way to place dummy transistors
Post by Berti on Oct 7^th, 2007, 10:25pm

Hi all,

back to layout ;)

Assuming I use a multi-finger layout sharing source/drain with enough dummies at each side. How do I tell that to the BSIM model?
I think the BSIM model just calculates the vth-shift depending on the number of finger of each device. Or do you use post-layout
simulations?

Regards

Title: Re: Is this a good way to place dummy transistors
Post by carlgrace on Oct 17^th, 2007, 10:24am

Berti,

Sorry for the late reply. You tell BSIM model about your dummies by increasing the SA and SB parameters in the model. They default to minimum for the process, which is the maximum stress condition. If you put SA=3.0u and SB=3.0u into your model cards, you will be able to simulate without layout extraction of the STI effect.

Carl

Title: Re: Is this a good way to place dummy transistors
Post by Berti on Oct 17^th, 2007, 10:21pm

Thank you Carl.
I found the parameters.

Title: Re: Is this a good way to place dummy transistors
Post by jimwest on Oct 19^th, 2007, 6:53pm

To Carl,
Is there any reason to set SA=3.0u and SB=3.0u ? How about 4.0u or 5.0u?
And is 3.0u a universal rule for all the process less than 0.13u?
Finally does the BSIM4 contain the STI effect, cuz I found the relevant model in the PDK?

Kinda Regards,

Jim