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Design >> Analog Design >> PSRR of Capless LDO
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Message started by ee10126 on Oct 11^th, 2007, 9:48pm

Title: PSRR of Capless LDO
Post by ee10126 on Oct 11^th, 2007, 9:48pm

I need to design an LDO which must be stable and function without an off-chip capacitor. Can I get a PSRR > 30 dB for frequencies beyond 1 MHz?

Thanks

Title: Re: PSRR of Capless LDO
Post by tosei on Oct 14^th, 2007, 8:53pm

Hi,

Your PSRR at frequencies above 1Mhz will mainly depend on your DC open loop gain and the dominant´s pole frequency: the higher frequency the dominant pole is located at, the better PSRR at higher frequency. In other words, you´ll need a large GBW loop.

Regards
tosei

Title: Re: PSRR of Capless LDO
Post by jimwest on Oct 19^th, 2007, 7:21pm

To Tosei,
Usually the LDO system cannot be simplized as one-pole system.
There are dominat pole non-dominat pole and compensate zero within the unity gain bandwidth.
Among them the dominat pole is much lower than 1MHz.
So the upper limit of the PSRR determins by the distance between the zero and the dominant pole.

K/R,

Jim

Title: Re: PSRR of Capless LDO
Post by lightgo on Nov 9^th, 2007, 5:57am

psr>30dB for all frequence?