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Design >> Mixed-Signal Design >> How to test the AD in GPS chips
https://designers-guide.org/forum/YaBB.pl?num=1197447358

Message started by edward.yin on Dec 12^th, 2007, 12:15am

Title: How to test the AD in GPS chips
Post by edward.yin on Dec 12^th, 2007, 12:15am

Hi, in GPS chips, there is a 2 bit ADC to digitize the IF output and give MAG&SIGN output to the baseband part.
Then I see in Zarlink datasheets a clock is used to synchronize the MAG & SGIN to latched to the rising edge of the clk.
But, they use a 5.714M clk to latch a 4.309M signal when in theory the digital output should faithfully track the original IF signal and have a certain duty cykle about 30%.
I think for sampling it is impossible.
So here how do the ADC work?
And how to test whether the ADC works well?
Thanks!

Title: Re: How to test the AD in GPS chips
Post by Berti on Dec 12^th, 2007, 11:38pm

Sounds like sample rate conversion (SRC) is performed.

Regards

Title: Re: How to test the AD in GPS chips
Post by ywguo on Dec 13^th, 2007, 12:08am

Hi Edward,

Do you mean that the sampling rate is 4.309MHz?

Yawei