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Design >> RF Design >> PLL lock and negative Kvco
https://designers-guide.org/forum/YaBB.pl?num=1202151515

Message started by Visjnoe on Feb 4^th, 2008, 10:58am

Title: PLL lock and negative Kvco
Post by Visjnoe on Feb 4^th, 2008, 10:58am

Dear all,

Imagine there's a 'classic' PLL (3-state PFD/CP, LC oscillator, integer N diivder) which locks nicely.
Let's assume the Kvco of the LC oscillator equals +100MHz/V, meaning the VCO frequency and the VCO tune voltage
are related by a positive derivative (~when the tune voltage increases, the VCO frequency will also increase).

Now assume I leave the whole PLL the same, but negate Kvco to -100MHz/V, meaning that now the VCO frequency will decrease when the tune voltage increases.

My question now is: would the PLL still lock? I would say no, since when e.g. the PFD/CP is giving 'UP' pulses to increases the VCO output frequency, the PLL will now actually do the opposite, namely lowering the VCO frequency.

Therefore, I would say the PLL is unstable and will divert to a condition where the LF voltage is clamped to one of the supply rails.

The problem now is however that I have a nearly-ideal Simulink model which proofs me wrong (PLL still locks when I negate the VCO gain).

Does anyone have any comments on this?

Kind Regards

Peter

Title: Re: PLL lock and negative Kvco
Post by loose-electron on Feb 4^th, 2008, 11:09am

If you flip the K of the VCO over in polarity, changing the charge pump polarity output should make the system work properly again.

You flipped the polarity of two things so the net result cancels out.

I would take a close look at your model definition, it wouldnt surprise me if you have something in there taking the absolute value, or something else where the model is not defined as expected.

-- The simulation results are only as good as the model being simulated, otherwise GIGO.

n'est-ce pas?

:D

-- Jerry

Title: Re: PLL lock and negative Kvco
Post by buddypoor on Feb 4^th, 2008, 12:23pm

Hello Peter,

some time ago I have made the same observations.
However, after change of the KVCO sign the PLL will never lock in the linear model (with phases as inputs). That is quite clear since – in this case – we will have a positive feedback with saturation.
But the nonlinear simulation model of the PLL (in my case with a multiplier PD) works properly for both signs.
However, the begin of the pull-in process will be different for both signs.
If the VCO frequency is lower than the reference (and KVCO positive) the pull-in process starts with an increase of the VCO frequency (with a positive control voltage).
In the other case (KVCO negative) the pull-in process first shows a decrease of the VCO frequency (with a negative control voltage).
But in both cases there is a similar beat frequency which slowly changes the VCO towards the reference frequency.
By the way, I like VISSIM for control system simulations.

Lutz

Title: Re: PLL lock and negative Kvco
Post by Visjnoe on Feb 4^th, 2008, 11:50pm

Dear all,

Thank you for your inputs. They confirm what I was thinking.
Jerry, I totally agree with you on the GIGO :)

Since my reasoning does not align with the model, I started questioning the model (and asked the question on the forum).
Every analog designer should be paranoi and suspicious in my opinion... :)

Kind Regards

Peter

Title: Re: PLL lock and negative Kvco
Post by Visjnoe on Feb 5^th, 2008, 8:35am

Dear all,

I have indeed found a stupid bug in my Simulink model. Theory/reasoning and my model are now in sync, as they should be.

Kind Regards

Peter

Title: Re: PLL lock and negative Kvco
Post by khouly on Mar 24^th, 2008, 7:01am

also i noticed this model , just to make things work , all u need to do cross over the up and down signal coming from PFD to CP , this will invert the -KVCO and things will work nicely

khouly