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Design >> Analog Design >> LDO error amplifier selection
https://designers-guide.org/forum/YaBB.pl?num=1219200978

Message started by trashbox on Aug 19^th, 2008, 7:56pm

Title: LDO error amplifier selection
Post by trashbox on Aug 19^th, 2008, 7:56pm

Hi all,
In general, error amplifier in LDO is one-stage amplifier and its output impedance is not very large, so the LDO's dominant pole is at LDO's output, not error amplifier's output, and a large capacitor (uF) at LDO's output is needed to reach it.

Why not use folded-cascode as error amplifier? It can make the amplifier's output be the dominant pole even there is pF capacitor at LDO's output. The advantage are:
1) no need large capacitor(uF) at LDO's output.
2) though the bandwidth is smaller, the larger loop gain can reach a better PSRR

Thanks!

Regards,
Trashbox

Title: Re: LDO error amplifier selection
Post by buddypoor on Aug 20^th, 2008, 3:37am

I think, the output capacitor is always necessary to cover sudden load changes - independent on stability aspects.
However, of course there other alternatives to stabilze the circuit by introducing a zero at a suitable frequency.
For example, look at the proposed method as described in the attached paper.
Regards

Title: Re: LDO error amplifier selection
Post by Berti on Aug 20^th, 2008, 4:36am

Hey buddypoor,

I consider using the compensation scheme from silva-martinez in a LDO implementation (without external cap).
Have you ever implemented a chip using this technique?
Can you give me some useful suggestions?

Thank a lot, regards

Title: Re: LDO error amplifier selection
Post by buddypoor on Aug 20^th, 2008, 6:13am

Berti wrote on Aug 20^th, 2008, 4:36am:

Have you ever implemented a chip using this technique?
Can you give me some useful suggestions?

Hi Berti,
I´m sorry, but up to now I was not involved in designing or implementing a chip like this. I´m engaged more or less only on a system level - and viewing your problem under this aspect it was clear for me that a frequency compensation scheme could be implemented also around the error amplifier.
Regards

Title: Re: LDO error amplifier selection
Post by nanion on Aug 20^th, 2008, 7:56am

I think folded cascode error amp is a good choice. For the compensation one can use the good old miller cap across the big pass device.
But this is all when using a PMOS pass device.

Title: Re: LDO error amplifier selection
Post by nanion on Aug 20^th, 2008, 8:03am

I didn't realize Buddypoor's paper already covers this. But then again its nothing but miller compensation. One has to be careful in this that depending on what Vout is required the poles can move a lot due to change in the capacitance/Rout.

Title: Re: LDO error amplifier selection
Post by trashbox on Aug 21^st, 2008, 10:13pm

Hi buddypoor,
Thanks for your reference. It seems good to produce a zero by VCCS instead of esr resistor. :-)

Regards,
Trashbox

Title: Re: LDO error amplifier selection
Post by buddypoor on Aug 22^nd, 2008, 2:21am

trashbox wrote on Aug 21^st, 2008, 10:13pm:

Hi buddypoor,
Thanks for your reference. It seems good to produce a zero by VCCS instead of esr resistor. :-)
Regards,
Trashbox

Hi trashbox,
I know that the paper I have posted is not complete.
Therefore I like to add the information, that - as a final conclusion - the paper did propose to place a capacitor across R2 in order to produce a zero in the frequency response of the loop gain.

Title: Re: LDO error amplifier selection
Post by thechopper on Aug 24^th, 2008, 4:55pm

nano_RF wrote on Aug 20^th, 2008, 7:56am:

I think folded cascode error amp is a good choice. For the compensation one can use the good old miller cap across the big pass device.
But this is all when using a PMOS pass device.

mmmm...the pass transistor stage does not usually have a large gain. Two reasons:

1) The LDO can work with such pass transistor in triode mode....
2) Even in saturation mode, the load is not large enough in order to provide a large (and constant) gain.

Therefore, I would not try to use a Miller compensation scheme across the pass transistor, but rather try to do it on the error amplifier if possible.

Regards
Tosei

Title: Re: LDO error amplifier selection
Post by nano_RF on Aug 24^th, 2008, 7:54pm

Quote:

Thanks for pointing it out. Depending on application pass devices can be very big. Lets say it wants to deliver 2 Amp with minimum Ron possible. In this case they can be High gain stage. Being such a big device it already makes the error amp to be in load compensated mode.

I am not sure what you mean by that LDO can work in triode mode (you are inferring that it will not work similarly for miller compensation on pass device).

In both cases we are trying to stabilize the feedback loop. Now lets say Pass device get in to triode region then performance will degrade no matter where you compensate it. Basically if pass device being in triode makes the loop broken then it will be the case for both way of compensation. All the error will keep accumulating on the gate node of pass device.

You are right in saying that it is not a constant gain stage and thus compensating this way can make PM or GM move alot depending on the gate bias.

Title: Re: LDO error amplifier selection
Post by Berti on Aug 25^th, 2008, 8:18am

Hello everybody,

Thinking a little bit I came to the conclusion that also the output impedance of the regulating amplifier might change substantially because a different vgs of the pass transistor (vs current, input voltage etc).
The dominant pole will therefore change, too.
Can there be something done to prevent that?

Cheers

Title: Re: LDO error amplifier selection
Post by thechopper on Aug 26^th, 2008, 6:51pm

nano_RF wrote on Aug 24^th, 2008, 7:54pm:

I am not sure what you mean by that LDO can work in triode mode (you are inferring that it will not work similarly for miller compensation on pass device).

Hi,

Sorry I was not clear but actually I meant the pass transistor entering in triode region as you correctly inferred.

Under such condition the loop gain will be smaller and therefore stability will be relaxed.
The main problem is when the pass transistor is under saturation mode, and specially for very large pass transistors driving large load currents as you pointed out. The reason for this is the large VGS associated to this device pushing this (usually relative high frequency) pole down to the dominant pole range.

Bottom line, increasing the error amplifier gain most probably will play against stability.

Berti: I totally agree with you if the design relies on the dominant pole being set by such stage and I doubt something (easy) can be done about it

Regards
Tosei

Title: Re: LDO error amplifier selection
Post by engronger on Sep 4^th, 2008, 7:22am

no capacitor LDO is not easy realized, since for a LDO driving large current(mA level) , its output pole can drift in a very large range(several Hz to KHz), so usually we design the output as the dominant pole.

trashbox wrote on Aug 19^th, 2008, 7:56pm:

Title: Re: LDO error amplifier selection
Post by engronger on Sep 4^th, 2008, 7:26am

i am afraid not, you know the pass element device's gate has a big capacitance. and the cascode configuration's drive ability is not enough

nano_RF wrote on Aug 20^th, 2008, 7:56am:

I think folded cascode error amp is a good choice. For the compensation one can use the good old miller cap across the big pass device.
But this is all when using a PMOS pass device.

Title: Re: LDO error amplifier selection
Post by nano_RF on Sep 4^th, 2008, 8:06am

Hi,

[//quote author=engronger link=1219200978/0#13 date=1220538374]i am afraid not, you know the pass element device's gate has a big capacitance. and the cascode configuration's drive ability is not enough.//quote]

Thanks for your point. But I guess without knowing the real spec requirement this is open to as many configuration as you want.

(1) First of all one needs to choose NMOS or PMOS diff pair. PMOS input pair is usually the choice since your ramping voltage is reference to ground.

(2) Depending on what error voltage is allowed. Say if you want LDO output voltage to be withing such and such error voltage. this will determine the required open loop gain for your set up. And will contribute to your Error amp choice.

(3) Now how big a pass device you are using depends on the Load current , and RON requirement. If you become worried about slew rate, then I am afraid you may need to go for high slewing opamp as an error amp. In other words Class A-B kind of amplifier, which will ensure that you have same pushing and pulling ability. And do get a similar ramp up and ramp down performance.

(4) You will need to use a cap at LDO output to make it as a RF short assuming this LDO is essentially providing current for an RF amplifier.

(5) And not to mention that bandwidth of the loop is related to your ramping up and rampig down profile. You need to know this spec as well.

(6) The RC corner of the Vramp input is also need to be set such that it is not passing the noise at the LDO output which will directly appear as noise at the loaded amplifier output. And depending on the number of stages this LDO is connected to can have AM and PM noise component as well.

This is a healthy discussion. Please feel free to provide feedback as deemed necessary.

Thanks

Title: Re: LDO error amplifier selection
Post by trashbox on Sep 7^th, 2008, 10:46pm

buddypoor wrote on Aug 22^nd, 2008, 2:21am:

trashbox wrote on Aug 21^st, 2008, 10:13pm:

Hi buddypoor,
Thanks for your reference. It seems good to produce a zero by VCCS instead of esr resistor. :-)
Regards,
Trashbox

Hi buddypoor,
What do you mean it is not completed?

My simulation shows it can produce a zero as the paper described though there is some magnitude peaking in frequency response,and these peaking is far away from the poles and zero.

Title: Re: LDO error amplifier selection
Post by buddypoor on Sep 8^th, 2008, 12:00am

trashbox wrote on Sep 7^th, 2008, 10:46pm:

Hi buddypoor,
What do you mean it is not completed?

The text ends abruptly - with other words: the last part of the paper is missing. This is what I ment with "not complete".

Title: Re: LDO error amplifier selection
Post by trashbox on Sep 8^th, 2008, 7:09pm

Hi buddypoor!
Thanks for your reply. I can download this paper at IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—I: REGULAR PAPERS, VOL. 51, NO. 6, JUNE 2004

Regards
Trashbox

buddypoor wrote on Sep 8^th, 2008, 12:00am:

The text ends abruptly - with other words: the last part of the paper is missing. This is what I ment with "not complete".

Title: Re: LDO error amplifier selection
Post by imd1 on Sep 9^th, 2008, 12:51am

trashbox wrote on Sep 8^th, 2008, 7:09pm:

The text ends abruptly - with other words: the last part of the paper is missing. This is what I ment with "not complete".

You can just get the final paper from here,
http://amsc.tamu.edu/SIS/Publications/pub/jounal/2004_6.pdf