The Designer's Guide Community Forum

The Designer's Guide Community Forum
https://designers-guide.org/forum/YaBB.pl
Design >> Analog Design >> subthreshold slope parameter n
https://designers-guide.org/forum/YaBB.pl?num=1224838828

Message started by PalmRunner on Oct 24^th, 2008, 2:00am

Title: subthreshold slope parameter n
Post by PalmRunner on Oct 24^th, 2008, 2:00am

Hello all,

Before asking my question, could someone give me a reference or expression about Id for transistor operating in subthreshold. In the books I have it is assumed that Vbs = 0. Unfortunately it is not so in my case, so I am looking for more complete equation to better understand the influence from the bulk.

Now to the question: it is about the subthreshold slope parameter ‘n’ which appears in the equation for Id. I have a circuit, which shows big device to device spread on a silicon especially at low temperatures. I tried to reproduce this behavior on a simulation with no success until now - MC simulation shows much less spread of the output. The point is that the output is directly proportional to ‘n’ and I suspect that namely ‘n’ is the main source of spread. From a simulation I extract n=1.27 and run Spectre Process&Mismatch MC analysis on it. The result tells me that the parameter ‘n’ has almost no process, temperature and device to device variations, which is quite doubtful in my eyes. My question is: Could it be that this factor ‘n’ is really so stable over different devices (and I have to look for the problem on another place) or it is simply not properly modeled in Monte Carlo?

Thanks in advance!

Title: Re: subthreshold slope parameter n
Post by raja.cedt on Oct 24^th, 2008, 3:09am

hi,
u can get the expression in vlsi devices by taur and ning text book.or simply introduce body effect in VTH,and substitute VTH id expression.But this expression wont for most simulation becaz lot of short channel effects.
Coming to u r question N is depends on Cox and Cdep.so there is lot process dependence(tox),voltage dependence(Cdep),Cdep also depends on doping of the substrate,temp(mobility in Cdep expression). But i dont know how u r getting results are nonindependent on PVT variations.
Thnak you

Title: Re: subthreshold slope parameter n
Post by Berti on Oct 24^th, 2008, 3:33am

"Tradeoffs and Optimization in Analog CMOS Design" by David M . Binkley is an other good book on device modeling using the EKV MOS model.

Title: Re: subthreshold slope parameter n
Post by PalmRunner on Oct 24^th, 2008, 6:10am

Thanks for the references. I’ll try to find these books.

I also think ‘n’ should be more process/temperature dependent parameter. If its spread is poorly modeled then I would get too good results from the simulator.
The actual (+-3 sigma) variations I get for ‘n’ are about +/-2.8% over all process corners and full temperature range (-40-120)
Currently I have only nominal silicon in hand, which means that only device to device variations are measured. Running “mismatch only” MC at nominal process and temperature I get only +/- 0.1% variations for ‘n’. Could it be that ‘n’ is really so constant parameter over one complete wafer? Or simply there is no statistical model for this parameter?

Thanks!