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Design >> Analog Design >> leakage in 0.13u process
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Message started by hugh on Oct 30^th, 2008, 8:07pm

Title: leakage in 0.13u process
Post by hugh on Oct 30^th, 2008, 8:07pm

Hi all,

I'm designing a PLL and using the tsmc 0.13G process. But the gate leakage current is about 1nA/um^2 for NMOS. So when using nmos as capacitors what should I do?

Another question is the Ioff is also high, 500pA for NMOS of 10/0.13. So the power down current for a large scale digital circuit is also very high, I guess about 100uA for about 200K gates. How to solve this?

Some suggest to use the 0.13 LP process. However I heard the leakage current is more severe in 90nm, and since we will migrate to 90nm later, I think we'd better solve it now.

Thanks for any suggestions,

Hugh

Title: Re: leakage in 0.13u process
Post by Monkeybad on Nov 3^rd, 2008, 12:45am

Hi! hugh
You can use the 3.3V NMOS rather than the 1.2V for the low pass filter capacitances. The leakage current of 3.3V NMOS is much smaller than the 1.2V.

Title: Re: leakage in 0.13u process
Post by hugh on Nov 3^rd, 2008, 2:30am

Thanks, Monkeybad.

But the cap density of 3.3V device is about 3 times lower, the area cost will be high. Is there any circuit techniques possible?

B.R.,

Hugh

Title: Re: leakage in 0.13u process
Post by Monkeybad on Nov 3^rd, 2008, 7:14pm

Some papers discuss using another charge pump to compensate the leakage current. Here is one of these papers I've found before. But it uses 90nm process.
"A 1-4 Gbps quad transceiver cell using PLL with gate-current leakage compensator in 90nm CMOS"
In my design I use the 3.3V device to solve this problem. The area cost is acceptable for my application now.

Title: Re: leakage in 0.13u process
Post by Berti on Nov 4^th, 2008, 3:49am

Hi,

I think that the gate leakage of 1nA/um2 is for vgs=1.2V. If your voltage at the gate is lower leakage will reduce, too. Maybe then it is ok for you design.
Otherwise you could also think about MIM/metal caps...

Regards

Title: Re: leakage in 0.13u process
Post by hugh on Nov 5^th, 2008, 3:56am

Thanks, Monkeybad & Berti.

Now I think the gate leakage can be handled by careful design.
What about the off state current? Our SoC has about 2M gates. And the power down current is now about 500uA, unacceptable. I think the only way is to power down the LDO for digital circuits also. But this need the support of system vendor. :(
Any suggestions?

B.R.
Hugh

Title: Re: leakage in 0.13u process
Post by Berti on Nov 5^th, 2008, 10:15pm

If no high-Vt devices are available you could power the digital core at a lower
supply voltage....if you timing constraints allow for that.
You will need level-shifter for the outputs, but the leakage will reduced a lot.

Cheers

Title: Re: leakage in 0.13u process
Post by hugh on Nov 6^th, 2008, 3:20am

Berti wrote on Nov 5^th, 2008, 10:15pm:

Really good idea. Also some paper point to this way.

Many thanks.

Title: Re: leakage in 0.13u process
Post by Tlaloc on Nov 6^th, 2008, 8:14am

I have also heard of a very large switch being put in series with the supply to power down portions of logic that are not being used. Of course, it would still leak if you are using the same type of device, but since it would be a PMOS, you should come out ahead. Using a higher Vt device--with the larger area--would also reduce the leakage.