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Design >> Analog Design >> method to decrease Vth of pMOS?
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Message started by trashbox on Nov 25^th, 2008, 4:15am

Title: method to decrease Vth of pMOS?
Post by trashbox on Nov 25^th, 2008, 4:15am

I'm design a large output current linear LDO with pMOS as pass element and want to save area by using small W/L pMOS.

Is there any method to decrease pMOS Vth? Thanks!

Trashbox

Title: Re: method to decrease Vth of pMOS?
Post by ACWWong on Nov 25^th, 2008, 6:58am

you could bias the back gate at ground...

Title: Re: method to decrease Vth of pMOS?
Post by thechopper on Nov 25^th, 2008, 6:44pm

Hi,

You could try biasing the body of the pass transitor about 200mv below the supply voltage.

What is the min drop out you need for you app? Depending on the drop out the pass transistor migth not need to be super large. You could eventually allow the pass transistor to enter into triode region without major consequences since usually the pass transistor stage does not gain too much, even when working in sat region (since usually the load is very small to achieve large gains).

Hope this helps
Tosei

Title: Re: method to decrease Vth of pMOS?
Post by trashbox on Nov 26^th, 2008, 2:00am

Hi ACWWong!
You idea inspires me! But it really dangerous. Haha..

Hi Tosei!
Thanks very much for your replying my questions always.I will try it. :)

Regards,
William

Title: Re: method to decrease Vth of pMOS?
Post by raja.cedt on Nov 26^th, 2008, 9:46pm

hi tosei,
i have a question regarding u r ans. from gain point of view it doesn't matter whether pass transistor is working in sat or triode(as you said,provided ldo is heavyly loaded),but from supply noise point of view if it is triode it will pass most of the noise to output. correct me if i ma wrong.
hi trashbox,
the following paper might help you,they have implemented same idea(more or less using body terminal,but its prone to forward biasing)

36 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 33, NO. 1, JANUARY 1998
A Low-Voltage, Low Quiescent Current,Low Drop-Out Regulator
Gabriel A. Rincon-Mora, Member, IEEE, and Phillip E. Allen, Fellow, IEEE

Title: Re: method to decrease Vth of pMOS?
Post by thechopper on Nov 27^th, 2008, 3:52am

Hi raja,

That is correct and a very well known trade off: minimum drop out voltage vs PSRR. If the pass transistor goes into triode region then PSRR is degraded.
My answer just pointed to optimize the minimum operation supply voltage withouth considering PSRR issues.

Regards
Tosei

Title: Re: method to decrease Vth of pMOS?
Post by raja.cedt on Nov 27^th, 2008, 9:14pm

hi tosie,
thanks for your answer.can please tell me is there any advantage of pass transistor in triode apart from low drop(may be i guess stability may improve).can you give any reference based on this?
Thank you.

Title: Re: method to decrease Vth of pMOS?
Post by loose-electron on Dec 5^th, 2008, 1:48pm

In a semi serious suggestion:

Change the threshold implant doping density in the channel, under the gate. It is generally the ion implant stage after after photo resist for the transistor body and prior to the gate polysilicon. Higher temperature or longer implant time period should result in a lower threshold voltage.

:D

Now the big question - Can you control the foundry? ;D
-- Jerry

Title: Re: method to decrease Vth of pMOS?
Post by PalmRunner on Dec 5^th, 2008, 2:55pm

Possible way to decrease the threshold voltage is to connect the bulk to the gate. This is so the called DTMOS device (Dynamic Threshold MOS). You have to be careful with the operating point of such device, because the bulk is slightly forward biased.

Regards,
PalmRunner

Title: Re: method to decrease Vth of pMOS?
Post by SATurn on Dec 10^th, 2008, 2:06pm

Hello,

Well, the must effective way is to bias the bulk of the transistors. In a PMOS device, by reducing the bulk voltage you can reduce the device VTH. Ofcourse you need to make sure that the SB junction will not be forwarded. The other possibility is increasing the length of transistor that can help to reduce the VTH a little bit (revese short channel effect).

SATurn