The Designer's Guide Community Forum

The Designer's Guide Community Forum
https://designers-guide.org/forum/YaBB.pl
Design >> Analog Design >> Intrinsic gain simulation
https://designers-guide.org/forum/YaBB.pl?num=1230406069

Message started by roger123 on Dec 27^th, 2008, 11:27am

Title: Intrinsic gain simulation
Post by roger123 on Dec 27^th, 2008, 11:27am

Hello all,

I am trying to generate intrinsic gain vs gm-id plots for 0.18um nmos and pmos devices. However, I am noticing that intrinsic gain for pmos is greater than that for nmos. I guess it should be the other way around. I would be grateful if someone could point out the error in my simulations.

Setup for nmos device
VGS = 0 to 1.8V, VDS = 0.9V

Setup for pmos device
VSG = 0 to 1.8V, VSD = 0.9V