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Design >> Analog Design >> 90 nm topology rules
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Message started by Shlapenka on Nov 14^th, 2009, 2:09pm

Title: 90 nm topology rules
Post by Shlapenka on Nov 14^th, 2009, 2:09pm

Greetings everyone!

I am looking for some papers on 90 nm layout (topological) rules. Anyone could help? Beem searching for some time now but cant find anything decent... One person sugjested to register at pdk.cadence.com, i tried but my account didint get aprooved, gues not everyone is able to get one. Im realy in need of this, for my course project, would be very thankful for some help!

Thank you!

Title: Re: 90 nm topology rules
Post by Mayank on Nov 15^th, 2009, 2:33am

Hello,
What exactly do you mean by topological rules ? If you are referring to layout design rules, then study the DRM [design rule manual] provided with your pdk......
If you want to know good layout techniques for processes below 90nm, refer to some text books / google it....You will find a lot of stuff on it....say ee214 course of stanford...

--Mayank

Title: Re: 90 nm topology rules
Post by Shlapenka on Nov 15^th, 2009, 3:09am

thank you so much mayank, u got me on the right road :)

here is everything that i needed, just found it, posting it just i case anyone else needs:

http://bwrc.eecs.berkeley.edu/classes/icdesign/ee141_s08/resources.html

Tnx again :)