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Design >> Analog Design >> Oscillators - Phase Noise Degradation
https://designers-guide.org/forum/YaBB.pl?num=1259245788

Message started by Mayank on Nov 26^th, 2009, 6:29am

Title: Oscillators - Phase Noise Degradation
Post by Mayank on Nov 26^th, 2009, 6:29am

Hi,
I have designed a CML Voltage-Controlled Oscillator in 65nm process.
Without the bias ckt (using ideal voltage source), the Oscillator shows -55 dBc @ 10kHz.....
How much degradation can i expect in this Phase Noise when i add a bias ckt with Replica Biasing scheme ??

--
thanx
mayank.

Title: Re: Oscillators - Phase Noise Degradation
Post by loose-electron on Nov 26^th, 2009, 4:53pm

tough to say - sounds like the best thing you can do is get it down to transistors and run Spectre PSS and Pnoise analysis.

jerry

Title: Re: Oscillators - Phase Noise Degradation
Post by Mayank on Nov 27^th, 2009, 1:00am

Hi Jerry,
Already carried out a PSS/PNOISE simulation on one of my designs...Got +ve Phase Noise ie > 0 dBc values

......Had a long Discussion with one of the senior members, Pancho_hideboo in the rf_simulators forum starting from http://www.designers-guide.org/Forum/YaBB.pl?num=1050465395/0#8

...Seems like none of the simulators are able to give correct results for Phase noise below the line-width of the oscillator. Any fix for this ??

--mayank.

Title: Re: Oscillators - Phase Noise Degradation
Post by pancho_hideboo on Nov 27^th, 2009, 2:09am

Mayank wrote on Nov 27^th, 2009, 1:00am:

...Seems like none of the simulators are able to give correct results for Phase noise below the line-width of the oscillator. Any fix for this ??

I think an integration without including suspicious frequency region is still enough useful for evaluation of jitter or phase noise.