The Designer's Guide Community Forum https://designers-guide.org/forum/YaBB.pl Design >> Analog Design >> Sampling in AFE https://designers-guide.org/forum/YaBB.pl?num=1259308810 Message started by Mayank on Nov 27th, 2009, 12:00am

Title: Sampling in AFE Post by Mayank on Nov 27th, 2009, 12:00am Hi all,          I am currently working on an Analog Front End Design. According to Wimax specifications, I need to sample my ADC at 179.2 MHz instead of usual 160 MHz.... So I need to generate a fractional Frequency. Two ways :-- 1.  Fractional PLL -- frequency averaged out by the loop & i get nearly exact 179.2 MHz. 2.  Integer PLL with S-D Modulated Fractional Post Divider -- Basically Out of the Loop Fractional division with Sigma-Delta Modulation.  -- Provides a output clock whose Frequency varies around an average value of 179.2MHz  But the clock from solution 2 is not a clock with exact constant frequency of 179.2MHz as opposed to solution 1. Can such a clock with an average freq around 179.2 MHz but not exact, be used as a SAMPLING CLOCK for  ADC ??? --mayank.

Title: Re: Sampling in AFE Post by pancho_hideboo on Nov 28th, 2009, 11:09am I assume your ADC is not undersampling. Is this right ? Mayank wrote on Nov 27th, 2009, 12:00am: Can such a clock with an average freq around 179.2 MHz but not exact, be used as a SAMPLING CLOCK for  ADC ??? Solution 1 might be possible for your purpose. Assume IF signal is downconverted from RF by mixing with Fractional PLL based LO. Then assume ADC sampled by true 179.2MHz. This might be equivalent to the following. - IF signal is downconverted from RF by mixing with integer PLL based LO. - ADC sampled by Fractional PLL based 179.2MHz. I think reasonable estimation of SNR degradation due to sampling jitter is required for further proceeding.

Title: Re: Sampling in AFE Post by Mayank on Nov 29th, 2009, 8:48pm Hello Pancho,                 Quote: I assume your ADC is not undersampling. Is this right ? No, my ADC is a Delta-Sigma Converter. Quote: Assume IF signal is downconverted from RF by mixing with Fractional PLL based LO. Then assume ADC sampled by true 179.2MHz. This might be equivalent to the following. - IF signal is downconverted from RF by mixing with integer PLL based LO. - ADC sampled by Fractional PLL based 179.2MHz. I didnt understand these two assertions of yours clearly......Can you pls elaborate further ?? & What do you mean by Quote: Fractional PLL based 179.2MHz. ??  Doesnt a Fractional PLL average out the division ratio and give out a TRUE 179.2 MHz ?? thanx, Mayank.

Title: Re: Sampling in AFE Post by pancho_hideboo on Nov 30th, 2009, 3:05am Mayank wrote on Nov 29th, 2009, 8:48pm: & What do you mean by Quote: Fractional PLL based 179.2MHz. ??  Doesnt a Fractional PLL average out the division ratio and give out a TRUE 179.2 MHz ?? Average frequecny is 179.2MHz. It has much jitter due to modulation such as DeltaSigma.

Title: Re: Sampling in AFE Post by Mayank on Nov 30th, 2009, 3:11am Quote: Average frequecny is 179.2MHz. It has much jitter due to modulation such as DeltaSigma. but doesnt the Loop Filter in the Fractional PLL (with Fractional division inside the Loop) filter out the modulation & provide a true 179.2MHz ?? mayank

Title: Re: Sampling in AFE Post by pancho_hideboo on Nov 30th, 2009, 3:18am Mayank wrote on Nov 30th, 2009, 3:11am: [quote]but doesnt the Loop Filter in the Fractional PLL (with Fractional division inside the Loop) filter out the modulation & provide a true 179.2MHz ?? Observe clock signal by using actual Oscilloscope. Do you understand requirements of sampling clock jitter for achieving target SNR in ADC ?

Title: Re: Sampling in AFE Post by Mayank on Nov 30th, 2009, 3:31am Quote: Do you understand requirements of sampling clock jitter for achieving target SNR in ADC ? If you are referring to my specs, Maximum allowable sampling jitter is 150ps pk-to-pk & 8ps rms for the ADC....

Title: Re: Sampling in AFE Post by pancho_hideboo on Nov 30th, 2009, 3:34am Mayank wrote on Nov 30th, 2009, 3:31am: Quote: Do you understand requirements of sampling clock jitter for achieving target SNR in ADC ? If you are referring to my specs, Maximum allowable sampling jitter is 150ps pk-to-pk & 8ps rms for the ADC.... I don't think you can achieve such small jitter by clock based on Fractional PLL.

Title: Re: Sampling in AFE Post by Mayank on Nov 30th, 2009, 3:35am Quote: Observe clock signal by using actual Oscilloscope. So you mean Fractional PLL with Δ-Σ loop divider doesnt average out the division ratio and give a true 179.2MHz ??    I had thought that Δ-Σ loop division will give true 179.2 MHz WHILE Δ-Σ post o/p divider outside the loop will give avg 179.2MHz....Was i mistaken ?? Is the Integer PLL the only way of getting true 179.2 MHz clock ??

Title: Re: Sampling in AFE Post by Mayank on Nov 30th, 2009, 3:42am Quote: I don't think you can achieve such small jitter by clock based on Fractional PLL. But Pancho, my problem is that with an Integer PLL + an i/p ref freq of 13MHz, to get an o/p clock of 179.2MHz i need to oscillate at 896MHz (896/5 = 179.2  & [896 Loop Division / 13 Ip Division] * 13MHz = 896), My problem is that for fcomparison frequency of 1MHz (because of i/p Division factor of 13), i have to keep PLL BW very Low(<100kHz by gardner's limit)....Hence, Oscillator phase noise dominates hugely.....Phase Noise requirements for VCO become - 60dBc@10k -- near LC performance...Difficult to obtain through ring Osci.... Is there any workaround or i have burn such high power to obtain - 60dBc@10k from a ring Osci mayank

Title: Re: Sampling in AFE Post by pancho_hideboo on Nov 30th, 2009, 3:43am Mayank wrote on Nov 30th, 2009, 3:35am: So you mean Fractional PLL with Δ-Σ loop divider doesnt average out the division ratio and give a true 179.2MHz ?? Average frequency is 179.2MHz. Mayank wrote on Nov 30th, 2009, 3:35am: I had thought that Δ-Σ loop division will give true 179.2 MHz WHILE Δ-Σ post o/p divider outside the loop will give avg 179.2MHz.... I can't understand what you mean. Mayank wrote on Nov 30th, 2009, 3:35am: Is the Integer PLL the only way of getting true 179.2 MHz clock ?? Strictly speaking, output of clock based on common dual-modulus PLL is also not clean. But it is far clean than clock based on Fractional PLL.

Title: Re: Sampling in AFE Post by Mayank on Nov 30th, 2009, 3:48am Quote: I had thought that Δ-Σ loop division will give true 179.2 MHz WHILE Δ-Σ post o/p divider outside the loop will give avg 179.2MHz.... I mean that --- 1.  if you use a fractional PLL with Δ-Σ modulation in loop divider --- that should give you a true 179.2 MHz clock because Loop Filter will filter out the Loop Division factor modulation, hence o/p will settle at a constant fractional frequency. 2.  If you use an integer PLL, and then do output clock's division in the post o/p divider employing Δ-Σ modulation, it should give you an average clock of 179.2MHz since the modulation is not filetered out... Are these statements incorrect ??? Quote: Strictly speaking, output of clock based on common dual-modulus PLL is also not clean. I dont understand what you mean by dual-modulus PLL.....And what idea do you have in mind to obtain a cleaner clock than an integer PLL ?? mayank.

Title: Re: Sampling in AFE Post by pancho_hideboo on Dec 5th, 2009, 4:35am Mayank wrote on Nov 30th, 2009, 3:48am: I dont understand what you mean by dual-modulus PLL..... And what idea do you have in mind to obtain a cleaner clock than an integer PLL ?? It is very very conventional. See http://www.national.com/analog/timing/pll_designbook

The Designer's Guide Community Forum » Powered by YaBB 2.2.2! YaBB © 2000-2008. All Rights Reserved.