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Design >> Analog Design >> level-shifter circuit
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Message started by casual on Jul 7^th, 2011, 5:44pm

Title: level-shifter circuit
Post by casual on Jul 7^th, 2011, 5:44pm

I found there is a lot of issue on standard level-shifter circuit during power up sequence check. The level shifter is a pmos cross-coupled type to level shift voltage vcc_low to vcc_high(2.5V).

could someone point me to some good papers or give me the design guide?

I try to use a weakpull down circuit to make the output deterministic during power up sequence.

welcome for discussion

Title: Re: level-shifter circuit
Post by raja.cedt on Jul 11^th, 2011, 10:06am

hi,
kind of issues you found during power up? means have you given input first and supply later or any thing else?

Thanks,
Raj.

Title: Re: level-shifter circuit
Post by wave on Jul 11^th, 2011, 2:19pm

It's a pretty classical issue.
(one of those you don't find in the text book).

Generally you hope most block control lines are immune to start up conditions, but inevitably there are a few sticklers.
PD, IDDQ, select lines, etc.

You can run your PoR signal in and give it a reset.
You have to look at your power, regulator turn on sequences carefully.

Wave
;)

Title: Re: level-shifter circuit
Post by casual on Jul 11^th, 2011, 6:19pm

i found issue and root cause it to the level shifter during power-up sequence (multiple power supplies). The issue is related to 'pd' signal
Will the PoR signal helps during power sequence ramping?

raja.cedt
all inputs are 0 because the vcc_low (core) is not up yet.

Title: Re: level-shifter circuit
Post by AnalogDE on Jul 12^th, 2011, 10:43am

You have a schematic you can show? It's hard to tell what's going on

Title: Re: level-shifter circuit
Post by RobG on Jul 14^th, 2011, 5:41pm

supermoment wrote on Jul 11^th, 2011, 6:19pm:

I take it that the output is undefined because of this. You could put a much weaker parallel NMOS driver pair in parallel with the main pair. You would drive this pair with a known signal, perhaps just a pull-up to the high supply that is pulled low by an NMOS with its gate tied to the lower supply?

Title: Re: level-shifter circuit
Post by harpoon on Jul 26^th, 2011, 7:48am

casual,
when vcc_low in not powered (or slowly ramping), the output can go either way depending on mismatch and other second/third order effects.

Here is what I think :-
a) Using POR signal to reset the relevant blocks is the best solution if your problem is simply the reset state further down the chain is not working. If the problem is something else, then the solution may be different.

b) RobG's suggestion sounds fair, just be careful of current consumption (driving low on a pullup will dissipate current)

c) Although I have not tried, you can put together a "startup" circuit like those used in bias blocks to hold one of the outputs high ? This circuit needs to be powered off vcc_2.5 of course. This way, the nodes will always be defined during startup.

Let us know what you come up with ... and also what your problem is exactly.