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Design >> Analog Design >> Id Vs Vd characteristic of NMOS and PMOS in saturation
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Message started by Larry_80 on Aug 2^nd, 2011, 1:33pm

Title: Id Vs Vd characteristic of NMOS and PMOS in saturation
Post by Larry_80 on Aug 2^nd, 2011, 1:33pm

Please i just need a confirmation if my reasoning for the below is correct
1.) For NMOS in saturation assuming the source voltage is kept constant and we increase the current flowing through an NMOS device, the drain voltage decreases.
Reasoning: In an NMOS, increasing the current flowing through implies an increase in the minority carrier (electrons) in the D-S channel thus the channel resistance reduces which means the Drain voltage should reduce.

2.) For PMOS in saturation assuming the source voltage is kept constant and we increase the current flowing through the PMOS device, the drain voltage increases.
Reasoning: In a PMOS, increasing the current flowing through implies an increase in the minority carrier (holes) in the D-S channel thus the channel resistance increases which means the Drain voltage should increase.

Please i need a verification of the above intuitive reasoning or a better way to look at it.

Thanks in advance for any expert opinion!

Title: Re: Id Vs Vd characteristic of NMOS and PMOS in saturation
Post by Larry_80 on Aug 2^nd, 2011, 1:59pm

Please any expert to clarify the above???

Title: Re: Id Vs Vd characteristic of NMOS and PMOS in saturation
Post by aaron_do on Aug 2^nd, 2011, 7:14pm

Hi Larry_80,

your understanding is incorrect.

In the saturation region, for a simplified model, the drain-source voltage is only dependent on the current flowing into the load and the load resistance (assume a common-source amplifier): when you increase the current flowing into the load resistor, the voltage across the load resistor increases, so if the supply voltage is fixed, then the drain voltage must drop. The drop in the drain voltage does not affect the current flow in the MOS because it is biased in the saturation region.

regards,
Aaron

Title: Re: Id Vs Vd characteristic of NMOS and PMOS in saturation
Post by Larry_80 on Aug 3^rd, 2011, 3:51pm

what if the load of the CS amplifier is a PMOS load in the case u have stated?

Title: Re: Id Vs Vd characteristic of NMOS and PMOS in saturation
Post by aaron_do on Aug 3^rd, 2011, 6:21pm

So now you asking the question for a common-source NMOS with a PMOS load? Can I assume the PMOS transistor is in saturation?

OK in this case, the simplified model doesn't work (i.e. the one where IDS is independent of VDS). In this case, any drain voltage which allows both NMOS and PMOS to be in saturation will be a correct solution to the problem. However, for a more realistic, but still simple model, IDS depends on VDS to a certain degree and this is shown in most basic analog texts (simplist reason is due to channel-length modulation). The easiest way to calculate the value of the drain-voltage of the transistor is to use a load-line curve. I drew an example below, but I kind of did it in a hurry, so sorry for the mess. Anyway, you can find this kind of example in some basic texts (See for example, Section 4.9 in Microelectronic Circuits by Sedra and Smith).

hope it helps,
Aaron

Title: Re: Id Vs Vd characteristic of NMOS and PMOS in saturation
Post by Larry_80 on Aug 3^rd, 2011, 6:25pm

Thanks a lot. It clears up all my confusion.