The Designer's Guide Community Forum

The Designer's Guide Community Forum
https://designers-guide.org/forum/YaBB.pl
Design >> Analog Design >> LDO with buffer
https://designers-guide.org/forum/YaBB.pl?num=1319660249

Message started by grosser on Oct 26^th, 2011, 1:17pm

Title: LDO with buffer
Post by grosser on Oct 26^th, 2011, 1:17pm

Hello

I wonder about using single stage opamp with unity gain buffer, but to achieve PM>60deg i need to lower amplifier's gain because the system is unstable in other case. Low current amplifier => smal transistors area => more offset => lower accuracy
Low gain influences load regulation badly.

What kind of amplifer do you use with unity gain buffer ? or what kind of buffer can i use. i tried source follower but the result is almost the same.

The second thing is, how ultra low quiescent current (1uA) LDOs are designed. The bandgap, amplifier, voltage divider consume current. How it's possible to make it so low and get quite resonable results?

kind regards

grosser

Title: Re: LDO with buffer
Post by rajkumar palwai on Oct 26^th, 2011, 10:10pm

Hi Grosser,
In all of the ultra low quiescent amplifiers, transistors are biased in sub-threshold and deep-subthreshold regions. In sub-threshold regions transistors are huge, currents are ultra-low and mosfets get highest gm's.

I dont understand why are u getting stablity problems by using a single stage amplifier. I dont see 2 poles here and hence the system should be stable.

Thanks
rajkumar

Title: Re: LDO with buffer
Post by grosser on Oct 27^th, 2011, 12:55am

rajkumar palwai wrote on Oct 26^th, 2011, 10:10pm:

I dont understand why are u getting stablity problems by using a single stage amplifier. I dont see 2 poles here and hence the system should be stable.

Thanks
rajkumar

Using one stage OTA biased at 1u for instance I cannot drive huge PMOS well. PM is very low then.

So I added the unity gain buffer to move dominant pole to higher freqs. Higher gain and pole movement makes the GBW 2 or 3MHz but the PM is still low for higher loads because of parasitics.

Title: Re: LDO with buffer
Post by raja.cedt on Oct 27^th, 2011, 1:01am

hello grosser,
is it an opamp or LDO (means single stage opamp and pass device), because you are talking about load current, so i am assuming that it's an LDo. So it's quite common to get stability problems. If you are using single stage opamp and still want to draw current better use some class AB stage.

@rajkumar: raj, i think because of two stage, he may get stability problem.

Thanks,
Raj.

Title: Re: LDO with buffer
Post by grosser on Oct 27^th, 2011, 1:42am

raja.cedt wrote on Oct 27^th, 2011, 1:01am:

Yes it's LDO design as the subject states.
I know stability problems, but want to know how to mix high gain amplifier >60dB with buffer and get PM>60. Everything with low currents <10uA overall

Title: Re: LDO with buffer
Post by raja.cedt on Oct 27^th, 2011, 1:54am

hello man,
i didn't understand term how ''to mix'', please remeber that gain and phase margin are not trade off you can any amount of gain for any decent phase margin..

Thanks,
Raj.

Title: Re: LDO with buffer
Post by grosser on Oct 27^th, 2011, 4:19am

raja.cedt wrote on Oct 27^th, 2011, 1:54am:

hello man,
i didn't understand term how ''to mix'', please remeber that gain and phase margin are not trade off you can any amount of gain for any decent phase margin..

Thanks,
Raj.

well, writting "to mix" i meant using high gain ota + buffer
no. i can't have any amount of gain with decent PM.
using high gain low current ota wit huge pass device you can't satisfy PM without compensation or buffering.

i'm asking for a clear advice regarding ota + buffer architecture, not "LDOs for dummies"

surely someone already did that.

Title: Re: LDO with buffer
Post by Praveen K on Oct 27^th, 2011, 5:33am

Hi grosser,

>>>>Using one stage OTA biased at 1u for instance I cannot drive huge PMOS well. PM is very low then.
>>>>So I added the unity gain buffer to move dominant pole to higher freqs. Higher gain and pole movement makes the GBW 2 or 3MHz but the PM is still low for higher loads because of parasitics.

you are adding a buffer here to drive the huge PMOS pass transistor, but anyway you are restricted by the power dissipation i.e. < 10uA.
why not you burn that in the OTA itself?

in PM point of view, this buffer is moving your dominant pole to higher frequency and hence worsens the phase margin. A buffer like this will only help, when the dominant pole is at the output of LDO( at drain of PMOS pass transistor).

my suggestion is, telescopic OTA ( burn the buffer current here itself), followed by PMOS pass and use miller cap through the cascode node of telescopic.

what say ;)

k.praveen

Title: Re: LDO with buffer
Post by loose-electron on Oct 27^th, 2011, 4:54pm

typically you want to use an OTA to drive the pass transistor.

sounds like you are using an op-amp structure?

Title: Re: LDO with buffer
Post by grosser on Oct 28^th, 2011, 1:20am

loose-electron wrote on Oct 27^th, 2011, 4:54pm:

typically you want to use an OTA to drive the pass transistor.

sounds like you are using an op-amp structure?

yes, but as low impedance output I use unity gain buffer

Title: Re: LDO with buffer
Post by analog_wiz on Nov 20^th, 2012, 2:52am

Grosser, can you post a pic of the arch you are trying to design. I have implemented some of these and can help you out.Standard LDO design topologies (according to me):

1. Differential to single ended stage followed by output stage which consists of a pass device sized to deliver current as per load current requirements.

2.Stb is entirely dependent on where your poles are. If your output pole is dominant then you will end up having movement of your dominant pole with load current (does the non dominant pole also vary:find out?)

3.Assume LDO is internally stabilized: then your worst case stability condition will arise when ILoad=0mA.In this case dominant pole is the standard pole due to miller cap due to pass device and the output pole is the gmpass/Cload+Cgd. You can burn very low current at the expense of being very noisy as well as at using up lot of area for your resistors(high res to due to low quiscent current). So if yours is not a noise critical application then you can maybe get away with burning very less current also.

More info once you let us know the application you are designing for... :)

Title: Re: LDO with buffer
Post by Lex on Nov 20^th, 2012, 5:37am

grosser wrote on Oct 26^th, 2011, 1:17pm:

I wonder about using single stage opamp with unity gain buffer, but to achieve PM>60deg i need to lower amplifier's gain because the system is unstable in other case. Low current amplifier => smal transistors area => more offset => lower accuracy
Low gain influences load regulation badly.
...

What kind of accuracy/PSRR are you looking for? What is the Iload(min) and Iload(max)?
"Lower current =>small transistor area" is not correct. Lower current => lower W/L.
Stability problems? Where are the poles and what kind of frequency compensation are you applying?