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Design >> Analog Design >> Problem about cml buffer with single-ended signal input
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Message started by Yutao Liu on Jul 24^th, 2012, 8:30am

Title: Problem about cml buffer with single-ended signal input
Post by Yutao Liu on Jul 24^th, 2012, 8:30am

Hello everyone,
One of the input of CML buffer is a sine wave and the other input is biased by a appropriate DC. How the output of the buffer should be?
I supposed that the waveforms of the output terminals are differential all the same.
But I found that the simulation result agrees with my thought only when the tail current source is an ideal current source (infinite output impedance). Why these happen? How the output impedance of the tail current source affect the outputs?

Thank you so much!

Yutao

Title: Re: Problem about cml buffer with single-ended signal input
Post by loose-electron on Jul 24^th, 2012, 12:14pm

Your signal processing is not purely diffferential.

The loading on/off due to the current source being real transistors to an ideal current source
changes the circuit from being a differential amplifier (ideal current source) to something that looks
like a pair of amplifiers with complementary signals being amplified. (non ideal current source)

Title: Re: Problem about cml buffer with single-ended signal input
Post by Yutao Liu on Jul 29^th, 2012, 1:25am

Thanks for the explanation.
I did a experiment.
When the current source is implemented by a resistor, the phase shift between two output signals approaches 180 degree as the resistor increase.
When the current source is implemented by a current mirror, the phase shift between outputs is always 150 degree or so. Is it possible that the parasitic capacitor of the current mirror (Cgd, Cdb ) induces another pole?

Yutao Liu

Title: Re: Problem about cml buffer with single-ended signal input
Post by raja.cedt on Jul 29^th, 2012, 4:59am

hello,
basically when you have fully differential input, current source don't impact much because tail node is perfect ac ground. When you have one input is sin and other one DC, tail node is no more ac ground hence tail current source impact a lot. Try to use cascode current source or single transistor with bigger length.

Thanks,
Raj.

Title: Re: Problem about cml buffer with single-ended signal input
Post by Annie on Oct 10^th, 2012, 7:27am

Raj,
I am designing CML Buffer in 65nm,1.1V MOS and for Current source I am using current mirror with larger L(~500n) to avoid short channel effects.However, the input swing to the buffer is not exactly small(~300mVpp),so the tail node is not exactly at ac ground at all times,rather it follows the higher input after switching takes place and so the vds of the current source changes and hence the tail current.Any hint to solve the problem?

Title: Re: Problem about cml buffer with single-ended signal input
Post by raja.cedt on Oct 10^th, 2012, 8:50am

hello,
show me the input and out waveforms including transistor current. it may trigger some thing..

Thanks,
raj.