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Design >> Analog Design >> low power opamp design problem
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Message started by lhlbluesky_lhl on Sep 15^th, 2012, 2:50am

Title: low power opamp design problem
Post by lhlbluesky_lhl on Sep 15^th, 2012, 2:50am

now, i want to design a very low power opamp (miller two-stage or symmetric single stage), what is the minimum value of branch current that can be accepted in normal 0.35um process?
if the bias current is 100nA (or lower) for every branch, what problems can be generated? and what considerations should be take for the low power opamp design? if the bias current is very small (nA order), then, what is the influence on offset, leakage, mismatch, and so on? can subthreshold leakage happen? besides, how is leakage current generated? is it related to body effect or subthreshold operation?

thanks all.

Title: Re: low power opamp design problem
Post by lhlbluesky_lhl on Sep 15^th, 2012, 7:11pm

is there any suggestion?

Title: Re: low power opamp design problem
Post by loose-electron on Sep 16^th, 2012, 8:10pm

start with some basic research.

Title: Re: low power opamp design problem
Post by analog_wiz on Nov 20^th, 2012, 8:19pm

You will be able to design with 10nA first stage and 100nA second stage. The design will go through. Some issues you will will need to live with:

1. Very low bandwidth(Hence very long settling time in case of coupling on critical nodes)

2. Low currents are good for input transistors noise performance but not for load transistors which need better vdsat's for better noise performance. The need to analyze all these will again depend on the particular application you are designing for.

You can refer holberg which has a nA opamp design. You should be able to find some more considerations there.