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Design >> Analog Design >> local LDO design for OSC
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Message started by lhlbluesky_lhl on Sep 28^th, 2012, 6:15am

Title: local LDO design for OSC
Post by lhlbluesky_lhl on Sep 28^th, 2012, 6:15am

i have designed a internally-compensated LDO for OSC module. as the ldo2.jpg shows, MP is the pass transistor, current is I1, current flowing RF1 and RF2 is I2, current flowing RL is I4, current flowing CL is I3. in my case, I4 is about 20uA, VO is 2V for 3V vdd input, after simulation, i found that, the charging current of CL (I3) is about 3uA, and so, the ripple voltage of VO is about 20mV. is this ok? and how is the charging current of CL generated? i want your explanation.
thanks.

Title: Re: local LDO design for OSC
Post by MillerStableCounty on Oct 4^th, 2012, 10:50pm

what simulation are you running? are you using moscap with gate leakage? i can't imagine why it can be sinking current at all. are you running a startup sim when the cap is charging up?

Title: Re: local LDO design for OSC
Post by lhlbluesky_lhl on Oct 5^th, 2012, 3:40am

yes, CL is MOS cap, and it is not a start-up sim, just the normal operation with the OSC core. how is the charging and discharging current of CL generated?

Title: Re: local LDO design for OSC
Post by boe on Oct 5^th, 2012, 9:34am

lhlbluesky_lhl,

your design seems to have a stability issue. An LDO output voltage should not oscillate with 20 mV amplitude without reason.

- B O E

Title: Re: local LDO design for OSC
Post by lhlbluesky_lhl on Oct 5^th, 2012, 8:11pm

so, what stability problem can it be, boe? is it the poor PM or any other reason? and the current of CL is 20uA, CL is 20pF mos cap, any problem?

Title: Re: local LDO design for OSC
Post by boe on Oct 10^th, 2012, 2:01am

lhlbluesky_lhl,

1) Probably. Note that only for all-pole systems PM is sufficient condition for stability.
2) The cap should have only (DC) leakage current. How large that can be depends on your technology.

- B O E

Title: Re: local LDO design for OSC
Post by Lex on Oct 10^th, 2012, 5:12am

If you have a ring oscillator your (current) load might look like an impulse train. If you model it like that, you might be left with some ripple.

But if this picture is exactly what you have simulated, then I'd guess I'd want it to be a bit more stable. Check the AC response to confirm whether you have some peaking.

Title: Re: local LDO design for OSC
Post by lhlbluesky_lhl on Oct 10^th, 2012, 6:57am

in my simulation, RL is actually an osc (current charging-discharging type), the load current for osc is almost constant (changing only a little). besides, in my ac response, there is a zero (used to improve high frequency psrr), can this zero cause the VO ripple? by hand calculation, the current of CL is 3uA or so, for 20uA load current, i think 3uA is a little big, but i don't know how to decrease it. CL is 20pF pmos cap, when i increase CL, the VO ripple decreases, but for area consideration, CL can not be larger than 20pF. is there any other suggestion or advice?

Title: Re: local LDO design for OSC
Post by lhlbluesky_lhl on Oct 11^th, 2012, 5:15am

in simulation, i found that, the VO ripple is also related to the load current. during the transition of each period, there is a current peak (200uA or so) for a normal load current of 20uA. if i decrease the current peak in simulation, the ripple also decreases. and the current peak may be caused by digital cells, such as inverter. and is this be ok?

besides, i uploaded the full diagram(1.jpg). RL is actually an osc, and LDO is used to suppress or decrease the power noise. but in simulation, i found that, when i add the power noise at vdd, the noise in VO is also very large, and so, the jitter of osc is ten times larger than non-power-noise case, why? is it related to the psrr+ of LDO? the psrr+ of LDO in low frequency is larger than 75dB. osc frequency is 4M here. why power noise not decreased as expected by using local LDO? is there any problem here?

thanks all for reply.

Title: Re: local LDO design for OSC
Post by boe on Oct 12^th, 2012, 4:38am

lhlbluesky_lhl,
Note that an LDO with pMOS pass transistor can only provide current pulses if the LDO is fast enough.
Also, LDO noise suppression only occurs at low frequencies.

- B O E

Title: Re: local LDO design for OSC
Post by lhlbluesky_lhl on Oct 12^th, 2012, 7:34pm

hi, boe, thanks for your reply. can you mean that my LDO circuit is ok?

Title: Re: local LDO design for OSC
Post by amarnathdinamani on Nov 13^th, 2012, 4:36am

Hi, i think your peak current requirement is more than what your output capacitor can supply. Actually if the oscillator is the only block sitting under this ldo,20mv should be ok. If you still wish to reduce this ripple which occurs because I=c*dv/dt,hence putting a bigger capacitor will lead to a smaller ripple at the output,but you need to ensure stability with a larger capacitor.Need some more details about your design before i can comment further.

Thanks