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Design >> Analog Design >> Is there any methods that can compensate the parasitics of the filter?
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Message started by unaffected on Oct 7th, 2012, 7:37pm

Title: Is there any methods that can compensate the parasitics of the filter?
Post by unaffected on Oct 7th, 2012, 7:37pm

I have designed analog filter for two years, I designed gm-C bandpss filters working at frequency about serveral MHz.

I am now amazed at how to design bandpass filter at serveral MHz with small ripple. For example, I choosed filter architecture, synthesize it and designed it , the simulation results show it has ripple with 1dB, but after I finished layout and do postsimulation, I found the ripple will changed into 2dB, and the filter bandwidth will also changed.

I think the change in bandwidth and ripple is because of parasitics, but I do not know how to compensate these parasitics  during the design process.

My question is : Is there any methods that can compensate the parasitics of the filter during the the design process of the filter? Or
please tell me where I can find papers or book talking about it.

Thank you very much.

Title: Re: Is there any methods that can compensate the parasitics of the filter?
Post by buddypoor on Oct 8th, 2012, 12:18am

Question: Are you speaking of passive or active filter topologies?
In general, compensation of parasitics certainly will nor possible.
Perhaps - reduction of its influence. However, in this case you have to know the value and the location of those parasitics. And thatīs the problem.
According to my knowledge, you only can reduce the influence of known deviations from the ideal case - like opamp non-idealitis and/or known deviations from nominal parts values (deviations from available standard values).

Title: Re: Is there any methods that can compensate the parasitics of the filter?
Post by unaffected on Oct 9th, 2012, 7:33pm

Thank you.

I am speaking of gm-C filters, is active filter.

Yes, I tried to reduce its influence, but because of the uncertaily of the parasitics and the limitation of the process, it is very difficult for me to fabricate a filter which have excellent performance.But when I see the
datasheet of some integrated bandpass filter (for example, IF filter in  receiver chip) which designed by some famous comany, its perfomance(bandwidth and ripple) is very good.

I am amazed at how can they fabricate filter with such good performance with the parasitics?
:)

Title: Re: Is there any methods that can compensate the parasitics of the filter?
Post by buddypoor on Oct 14th, 2012, 3:31am

According to my knowledge the most severe error source in gm-C topologies is the finite output impedance of the controlled current sources.

Title: Re: Is there any methods that can compensate the parasitics of the filter?
Post by weber8722 on Oct 29th, 2012, 7:05am

Hi, with circuit optimization techniques you can push back the changes of the real gmC filter compared to the idealized filter-prototype  :). Optimize the element values, i.e. gm and C. This way you should be able to get a near-ideal performance even with nonideal elements.
This is more difficult with op-amp based active filters because they really suffer from addional poles and zeroes. But also here there are some tricks, like adding a series R to the integration caps.

Bye Stephan

Title: Re: Is there any methods that can compensate the parasitics of the filter?
Post by buddypoor on Oct 29th, 2012, 8:55am


weber8722 wrote on Oct 29th, 2012, 7:05am:
Hi, with circuit optimization techniques you can push back the changes of the real gmC filter compared to the idealized filter-prototype  :). Optimize the element values, i.e. gm and C. This way you should be able to get a near-ideal performance even with nonideal elements.
This is more difficult with op-amp based active filters because they really suffer from addional poles and zeroes. But also here there are some tricks, like adding a series R to the integration caps.

Bye Stephan


"Circuit optimization" sounds rather good. Also the recommendation to "optimize the element values" is not a bad one.
With other words (in short): Simply compensate the errors. Fine.
However, where are the "tricks" to find optimized parameters?

Title: Re: Is there any methods that can compensate the parasitics of the filter?
Post by Lex on Oct 30th, 2012, 2:26am


unaffected wrote on Oct 7th, 2012, 7:37pm:
...
I think the change in bandwidth and ripple is because of parasitics, but I do not know how to compensate these parasitics  during the design process.

My question is : Is there any methods that can compensate the parasitics of the filter during the the design process of the filter? Or
please tell me where I can find papers or book talking about it.


Does your foundry provide a rule deck for parasitic extraction? Then extract your layout and just re-simulate and check how the parasitics influence your characteristics.

Title: Re: Is there any methods that can compensate the parasitics of the filter?
Post by Dan Clement on Oct 30th, 2012, 4:44am

The bandwidth of your gm cell should be much higher than your signal frequency.

The output impedance at dc should be as high as possible.

If neither is true then your integrators aren't really integrators and your transfer function will not work properly.

You should also plan on q reduction from parasitics by designing it high. Also don't forget bandwidth shrinkage if cascading filters.

Of course post layout simulations are required and expect some tweaking will be necessary.

Title: Re: Is there any methods that can compensate the parasitics of the filter?
Post by loose-electron on Oct 31st, 2012, 9:41pm


buddypoor wrote on Oct 14th, 2012, 3:31am:
According to my knowledge the most severe error source in gm-C topologies is the finite output impedance of the controlled current sources.



I do agree with that -

Beyond the less than ideal performance of the
transconductor, you can impedance scale  the
device so that parasitics are a smaller amount
of the performance criteria

Parasitics remain constant, and frequency defining
elements become a large part of the equation.

Even that fails however if you have to size scale up
your transistors to deal with higher currents required
to do impedance scaling.

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