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Design >> Analog Design >> two poles when the opamp in SC configuration?
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Message started by prcken on Nov 10^th, 2012, 7:56pm

Title: two poles when the opamp in SC configuration?
Post by prcken on Nov 10^th, 2012, 7:56pm

Hi All,
I did
1. opamp open loop simulation, folded cascode with and w/o gain boost
2. put the opamp into multiply-by-two configuration, do pss+pstb analysis, check the gain and unity freq.
3.in the open loop bode plot, DC gain of opamp with and w/o gain boosting is 66.7dB and 44.25dB, respectively. GBW is more than 500MHz and 700MHz, respectively.
4. in the SC configuration, the loop gain drops to 42.45dB and 33.45dB for with and w/o gain boosting, respectively, at 50MHz sampling rate, the GBW drops to ~56MHz and ~45MHz, respectively. seems has two poles there so that the slope falls faster.

I don't know how to add multiple pictures, i will add pictures separately.

AC sim schematic, CL=1.5p

Title: Re: two poles when the opamp in SC configuration?
Post by prcken on Nov 10^th, 2012, 8:09pm

pstb setup schematic, CL=1.1p, Cf=Cs=0.75p
use cmdmprobe, set CMDM=-1 for checking DM loop stability
in pstb, the gain drops a lot as you can see later. why is that? due to feedback factor?
the plots i got shown later is the cmdmprobe probed at front of CMFB in the opamp schematic.

Title: Re: two poles when the opamp in SC configuration?
Post by prcken on Nov 10^th, 2012, 8:10pm

folded cascode gain-boosted opamp schematic, 3mA current excluding gain-boosting opamps and bias generator.
two CMFB shown, one is ideal CMFB used for AC (continuous time) simulation.

Title: Re: two poles when the opamp in SC configuration?
Post by prcken on Nov 10^th, 2012, 8:17pm

bode plot, open AC sim and loop pstb sim plots.
black line: open AC sim with gain boosting
green: open AC w/o gain-boosting
purple: pstb sim with gain boosting (seem anther pole introduced?)
red: pstb sim w/o gain-boosting

seems opamp put into SC configuration, there have two poles?
I found it's really hard to increase GBW. by hand calculation, i should get 280MHz unity frequency. what I have got it's far less than 280MHz.
in open AC sim, more than 700MHz unity frequency doesn't means anything when i plugged the opamp into the application, why?
thanks!

Title: Re: two poles when the opamp in SC configuration?
Post by prcken on Nov 10^th, 2012, 9:35pm

I found a problem that after i added a pair of switch (yellow circle as i indicated), the result seems good now, enough GBW but smaller PM. as shown in the picture below.
i didn't add that pair of switch is because I intend to do opamp sharing in the pipeline ADC so that pair of switches will not be there in that case.
even without that switch, the input common mode voltage can still settles to around half vdd, but why it affect the speed that much? that means, when at sampling mode, the opamp has to be in unity feedback configuration?
any comments?

Title: Re: two poles when the opamp in SC configuration?
Post by urian on Nov 14^th, 2012, 6:33am

I think the GBW drops because the feedback factor is low. I dont know the arithmetic of pstb how it calculates the PM and GBW, so I dont know why when you add another pair switches, you will get better PM and GBW.
BTW, what's the purpose of NMOS below the input folded PMOS in the amp?

urian