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Design >> Analog Design >> Problem on ESD protection circuit with 5V CMOS
https://designers-guide.org/forum/YaBB.pl?num=1355638455

Message started by Yutao Liu on Dec 15^th, 2012, 10:14pm

Title: Problem on ESD protection circuit with 5V CMOS
Post by Yutao Liu on Dec 15^th, 2012, 10:14pm

Hello everyone,
I am designing an ESD protection circuitry with 5V 0.25um BCD technology. The supply voltage range is from 2.5V ~ 10V. Initially, I want to build a I/O pin ESD circuit with GGNMOS and a VDD-VSS ESD clamp with RC-triggered clamp. The drain-source breakdown voltage is 11V. The gate dioxide BV is nearly 20V but the maximum normal operation Vgs is 5V according to datasheet.
I have a few questions as following:
1. There is a inverter in the RS-triggered clamp. During normal operation, the input of the inverter is connected to VDD, so vgs of a NMOS in the inverter is always VDD. Is this a big problem in my design? How to solve this problem?

2. It is reported from the foundry that the first breakdown voltage of the ggNMOS is 11.8V and the holding voltage is 7.8V. I worry about that the holding voltage is so low that latch-up will comes out at the I/O pins. Should I really worry that? If so, how can I increase the holding voltage, or any other ideas?

Thanks!

Yutao Liu