The Designer's Guide Community Forum https://designers-guide.org/forum/YaBB.pl Measurements >> Phase Noise and Jitter Measurements >> Noise in PFD/CP https://designers-guide.org/forum/YaBB.pl?num=1037357676 Message started by Aigneryu on Nov 15th, 2002, 2:54am

Title: Noise in PFD/CP Post by Aigneryu on Nov 15th, 2002, 2:54am Dear Ken: I saw a PFD/CP phase noise profile in figure 7 in your paper (phase noise + jitter). It was illustrated that the Y-axis stands for Sphi which has a floor of n. But in the veriloga code provided below, n means the white noise current in A^2/Hz. Are these two things the same? I can simulate a PFD/CP and the output current noise spectrum could be found. Can I just divide it by (Kdet/2pi) to count the input refered phase noise?? :)

Title: Re: Noise in PFD/CP Post by Ken Kundert on Nov 17th, 2002, 9:51am Aigneryu,     Sorry, my mistake. The y-axis should be labeled SI (the power spectral density of the noise current). -Ken

Title: Re: Noise in PFD/CP Post by Aigneryu on Nov 17th, 2002, 6:52pm Dear Ken:  Both in section 5 and 9.1.2 which described the method to extracting the phase noise or jitter in PFD/CP, it was said that I should drive the PFD/CP with periodic signals with offset phase, and measure the output noise current spectrum. Isn't the output noise current spectrum correlated to the offset phase? If I drive the two input port of PFD with zero phase deviation, the output spectrum could go wrong? If so, why?  And in section 5, you said it is necessary to capture the noise during the switching process, it seemed you suggest us to use trobed noise analysis, but in section 9.1.2, you said that we should treat PFD/CP output noise as a contineous noise current. What is the difference between these two case? Or it's just because I made some mistakes in section 5? Finally, I would like to ask what's the bandwidth of PFD/CP that was mentioned in section 9.1.2? If I drived the PFD/CP in different frequency to extract the noise spectrum or jitter, should I take the frequency into consideration? For example, the input refered noise floor of PFD/CP at certain frequency could somehow differs from that driven at another frequency. If the noise floor of PFD/CP won't change with the frequency of the driving signal (or reference frequency), then the output phase noise of PLL in the loop bandwidth would probably be the input refered noise floor PFD/CP plus 20*log(N), where N means the main divider ratio. While documentations declared the input refered PFD/CP noise floor should be proportion to 10*log(Fref) in dB.  :)

Title: Re: Noise in PFD/CP Post by Ken Kundert on Nov 17th, 2002, 11:02pm Quote: Both in section 5 and 9.1.2, which described the method of extracting the phase noise or jitter in PFD/CP, it was said that I should drive the PFD/CP with periodic signals with offset phase, and measure the output noise current spectrum. Isn't the output noise current spectrum correlated to the offset phase? If I drive the two input port of PFD with zero phase deviation, the output spectrum could go wrong? If so, why? My feeling is that in most cases the noise will not vary substantially with the phase difference of the two input signals. In doing so I am implicitly assuming that the noise of the PFD/CP is dominated by jitter, which is independent of the phase difference between the inputs. But this is a judgment that can only be made by knowing the phase detector being used. For example, it may be that the jitter in the edges of the PFD/CP output pulses changes considerably between when the CP produces positive and negative pulses. If this is a concern, you should extract the noise for both cases and either use the worst case, or use more sophisticated models that includes the effect of both. At zero phase deviation, either positive and negative pulses are present simultaneously, or neither are present. Whichever, this is yet another condition that should be considered. Finally, if the noise of the PFD/CP is dominated by the noise in the amount of current produced rather than the jitter in the edges of the pulses, then you can expect the noise power to vary in proportion to the phase difference in the input signals. Again, in this case, a more sophisticated model is needed. Quote: And in section 5, you said it is necessary to capture the noise during the switching process, it seemed you’re suggesting the use of a strobed noise analysis, but in section 9.1.2, you said that we should treat PFD/CP output noise as a continuous noise current. What is the difference between these two cases? Or is it just because I made some mistakes in section 5? A charge pump when off generally produces very little noise at all. When on you also get the noise associated with the current it produces. And when turning on or off, you also see the effect of jitter. In section 5 where I said it is important to “capture the noise of the switching process”, what I as suggesting is that it is important to measure the noise at the output while the charge pump is producing pulses. If it is not producing pulses, you are not getting a realistic estimate of the noise it produces in practice. I was not suggesting that you use the strobed noise feature. Quote: Finally, I would like to ask what's the bandwidth of PFD/CP that was mentioned in section 9.1.2? It is the noise bandwidth of the PFD/CP. Thus, I assume that the input frequency is fixed, and I am measuring the bandwidth of the noise at the output of the CP. Quote: If I drive the PFD/CP at a different frequency to extract the noise spectrum or jitter, should I take the frequency into consideration? For example, the input referred noise floor of PFD/CP at certain frequency could somehow differ from that driven at another frequency. I did not consider the effect of frequency changes at the input of the PFD. It was my assumption that it would always operate at Fref, which was constant. If in your application Fref is variable, you might want to run experiments to see how the noise produced by the PFD/CP changes with input frequency. Quote: If the noise floor of PFD/CP won't change with the frequency of the driving signal (or reference frequency), then the output phase noise of PLL in the loop bandwidth would probably be the input referred noise floor PFD/CP plus 20*log(N), where N means the main divider ratio. While documentations declared the input referred PFD/CP noise floor should be proportion to 10*log(Fref) in dB.   I’m afraid I do not understand the second statement.

Title: Re: Noise in PFD/CP Post by Aigneryu on Nov 17th, 2002, 11:29pm Dear Ken:  Thank you to answer my questions with so great patience. :) And the last question is resulted from my carelessness, Haha, and I found it already :)  Thanks again

Title: Re: Noise in PFD/CP Post by jwang on May 20th, 2003, 4:02pm Hi, Ken or Aigneryu, Please let me know how you get the Sn in units of A^2 with spectre pnoise simulation? With output option set to probe or voltage, I always get the output noise with the units V/sqrt(Hz) or phase noise dBc/Hz. I am also wondering the load of charge pump for this simulation. Would you also confirm that if I can use Kdet = Ip wher Ip is the maximum charge pump current? Thanks. Jeff

Title: Re: Noise in PFD/CP Post by Ken Kundert on May 20th, 2003, 9:55pm Jeff,    To measure the noise density in a current, you must make the current flow through a voltage source or a current probe (iprobe). Then you must specify that vsource or iprobe as the output probe on the PNoise analysis form (do not specify output as a node or pair of nodes). Concerning whether Kdet = Ip, different phase types of phase detectors have different gains, so you must answer that question yourself for your particular phase detector. Are you suggesting that my paper is incorrect in giving Kdet = Imax (that for the type of phase detector I describe, the gain would not be such that Kdet = Imax)? -Ken

Title: Re: Noise in PFD/CP Post by jwang on May 21st, 2003, 12:31pm Hi, Ken, Thank you very much for such a quick response. No, I am not suggesting that Kdet = Imax is incorrect. Actually, I am using the same pfd architecture as described in your paper and using eq. 56 in your paper to extract the jitter numbers with Kdet set to Imax of charge pump. However, I encountered another problem. The pfd at my hand is running at 154K Hz. I have set max sideband to be 10 and sweeping freq from 1 to 100M. After squaring and integrating the noise output that is in units of A/sqrt(Hz), using eq. 56, I got Jee = 2.476n. I am using TSMC device model. The charge pump current is about 3.5u. The jitter number of 2.476n is too large to be true. I did two more experiment with smaller T. I got Jee = o.53n for T=1/1.54M and Jee = 60p for T=1/15.4M. As you said in a different place. Jitter is independent of T provided it is large enough to cover both rising and falling time. This is certainly the case for the circuit I am testing. Do you see anything I am doing wrong? How can I make sure that I have extracted the right jitter for the circuit under test? Best regards. Jeff

Title: Re: Noise in PFD/CP Post by Ken Kundert on May 21st, 2003, 10:09pm The first thing I suggest you do is get a handle on the value needed for maxsideband. Clearly using maxsideband=10 is too small when using the a period of 1/154KHz. I would shrink the period and increase maxsideband and play around with these two parameters until you are comfortable with the results. You might have a tendency to you a very large value for maxsideband, which is generally not needed. I recommend you read "Simulating switched-capacitor filters with SpectreRF" from http://www.designers-guide.com/Analysis/, particularly section 2.2.1 for an understanding of the trade-off between the maxsideband parameter value and speed and accuracy. -Ken

Title: Re: Noise in PFD/CP Post by Amit on Mar 3rd, 2005, 4:55am Hi Ken, I have following query regarding simulation setup for the charge pump current noise density.   1. What load do need to use for the charge pump nosie simulatuion, should it be actual loop filter or simple capacitor.   2. How much phase offset should be applied to the input of the PFD. Rather if we apply the phase offset at the input of the pfd pss analysis don't converges as the output voltage will vary continuous with time. How to tackle this issue -Amit

Title: Re: Noise in PFD/CP Post by Ken Kundert on Mar 3rd, 2005, 7:31am Amit,     The answers depend on the circuit being analyzed. Quote: 1. What load do need to use for the charge pump nosie simulatuion? Should it be actual loop filter or simple capacitor? If the noise produced by the charge pump is not strongly affected by its output voltage, you can simply drive a grounded voltage source or iprobe. For more realism and accuracy, you can drive the actual filter. Driving a capacitor that models the filter would be an intermediate approach. However, if you have an integrating charge pump/filter, you will have to eliminate the filter during this simulation in order to assure the output signal is periodic during the test. In this case, connect the output to ground through a voltage source or iprobe that allows you to measure the output current. Quote: 2. How much phase offset should be applied to the input of the PFD? The assumption I made in the paper is that the noise performance is independent of the phase offset. As the circuit designer, you will have to decide if that is a reasonable approximation. Quote: Rather if we apply the phase offset at the input of the pfd pss analysis don't converges as the output voltage will vary continuous with time. How to tackle this issue? I believe that this question implies that you have an integrating phase detector, so a constant phase offset results in an ever increasing voltage on the output if the filter is present. In this case, you should not include the output filter in the simulation. Just drive a grounded voltage source. -Ken

Title: Re: Noise in PFD/CP Post by Amit on Mar 3rd, 2005, 9:28pm Hi Ken, As mentioned in your previous message. I have following setup to measure the noise current of my differential charge pump. 1) I set the initial voltage at the charge pump output to vdd/2 (using .ic) 2) connected the voltage source with 0 dc voltage between two node. 3) Applied the phase offset at the pfd input. i am running the simulation with following setup. Quote: simulatorOptions options reltol=1e-3 vabstol=1e-6 iabstol=1e-12 temp=27 \    tnom=27 scalem=1.0 scale=1e-6 gmin=1e-12 rforce=1 maxnotes=5 maxwarns=5 \    digits=5 cols=80 pivrel=1e-3 ckptclock=1800 \    sensfile="../psf/sens.output" pss  pss  fund=526.3158M  harms=40  errpreset=conservative +    writepss="psk.pss"  method=gear2only  maxacfreq=100G tstabmethod=gear2only +    annotate=status highorder=no finitediff=no fullpssvec=yes pnoise  pnoise  sweeptype=relative  relharmnum=0  start=1M +       stop=1G  maxsideband=40  oprobe=V2 annotate=status Simulations converges but the problem is that i am finding noise current peaking at  higher frequency (above 10Mhz). This is exactly opposite to what mentioned in your paper. I don't know where i am making mistake. ??? Another query: I am calculating the variance of noise current using the noise summary utility where i am integrating the noise current from 10Hz to 1G. Is there any higher limit (As in my case var keep on increasing with increase in higher limit)? -Amit

Title: Re: Noise in PFD/CP Post by Ken Kundert on Mar 4th, 2005, 12:08am I recommend you get rid of the filter capacitors altogether and use two voltage sources connected to ground (with their voltage set to Vdd/2). Currently, the common-mode output voltage can drift, which could cause convergence difficulties (if it drifts, the output is not periodic and PSS does not converge). Do you know what the cause of the noise peaking is? I do not understand why it would peak at a frequency just above 10MHz. Concerning the upper limit on the noise analysis frequency, remember that your circuit does have a filter in it. Be sure to take that into account. You want to go to high enough frequency so that you can accurately predict the total noise at the output of the filter. -Ken

Title: Re: Noise in PFD/CP Post by rf-design on May 4th, 2005, 1:34am The method underlying the PFD-CHP simulations are not clear to me. I thought that the CHP noise is composed of two terms. 1. The shot noise from two canceling current sources. The two current sources are only active for a short time relative to the reference period. The equation would be in^2=(tactive/tref)*2*(2*q*Ichp), [A^2/Hz] if the both current sources are uncorrelated. I consider also noise folding effects but the circuit following the CHP will integrate the noise with a filter function. So the high frequency noise components will also be filtered. So the high frequency noise up to the noise bandwidth is not folded into the frequency band up to the reference frequency. It is filtered by the loop filter. So there is no noise folding. 2. The jitter noise of the control signals activating the current sources. This requires a periodic noise analysis. The output current should be split up in positive and negative current sources. So the periodic noise analysis could be made individual on both edges. Is this method correct to simulate the CHP noise effects?

Title: Re: Noise in PFD/CP Post by Ken Kundert on May 4th, 2005, 9:44am Concerning your first point, whether or not noise folding occurs is more an issue of how you model it. If you model the noise of the current source as a stationary white noise source modulated by the duty cycle of the transistor, then noise folding occurs and that folding is not affected by the filter because it occurs before the noise reaches the filter. In this case, the filter is filtering the already folded noise. If you think of the noise as being produced by a cyclostationary noise source, then you have already included the effect of the large modulation signal into the noise source, meaning that there is nothing left to modulate the resulting noise. So no folding occurs, because there is nothing else in the circuit that further modulates the already modulated noise. On your second point, you are not interested in measuring the jitter produced by the CP because the circuit that follows the CP is not a thresholding circuit. The circuit that follows the CP is a continuous time filter, and it is sensitive to noise produced over all time, not just at edge crossings.  So, if you are interested in the noise at the output then you must quantifiy it using the time-average power spectral density of the current (SI). It is possible to refer the noise back to the input of the PFD, in which case you would refer it back as a jitter since the input of the PFD is a thresholding circuit. -Ken

Title: Another question about  noise in PFD/CP Post by boa on May 12th, 2005, 11:29pm Dear all, I have extracted the output noise of PLL blocks using PNoise analyses as described in Ken's paper and built a linear phase-domain PLL model. The simulated results are pretty close to the measurements from the chip and the phase-domain model shows that the low-offset in-band phase noise of PLL is donimated by PFD/CP block. The CP is a simple single-ended charge pump with switch in source. I looked at the PFD/CP output noise contributors and the major noise was due to flicker noise of NMOS cascode bias transistors in CP which is logical. But after I increased the length of the bias transistors, the next major noise contibutors were transistors in the inverters which serve as buffers for the UP & DOWN signal between PFD and CP. The buffer is a chain of 2 inverters, so Cadence shows that noise comes from the NMOS in the second inverter. If I further on increase both W&L in the second inverter, then the major noise contributors are transistors in the 1st inverter!! I cannot explain such behavior - can this simulation results be realistic??? A few words about simulation setup: the PFD clock freq is 600 kHz, in PSS number of output harmonics is 30, in PNoise maxsideband=30, I am looking at noise at 1-10kHz. Another question is: for PFD/CP PNoise analyses, is it necessary to use "sweeptype" parameter "absolute" or "relative" (with the 1st relative harmonic)?

Title: Re: Noise in PFD/CP Post by brumby on Nov 1st, 2005, 2:20am Hi Ken all,      I met a problem as Amit mentioned on 03/04/05,       Quote: Simulations converges but the problem is that i am finding noise current peaking at  higher frequency (above 10Mhz). This is exactly opposite to what mentioned in your paper. I don't know where i am making mistake. ??? When run simulation to compute the jitter in PFD. The simulation is set as following: Quote: pss  pss  fund=100M  harms=20  errpreset=conservative  tstab=20n +    saveinit=yes  annotate=status pnoise  pnoise  start=1M stop=1G  dec=20  maxsideband=30 +         oprobe=V_MODIFIED  annotate=status The driving signal to PFD/CP is 100MHz, and in PNoise analysis, I sweep frequency from 1MHz to 1GHz , and finding a current peak noise at 100MHz. And the phase offset between reference and divider signal is 0.02ns.    Did I set the simulation correctly?

Title: Re: Noise in PFD/CP Post by brumby on Nov 1st, 2005, 4:41pm When I reset the Pnoise parameter to compute the noise from 99MHz to 101MHz with setup 0.04MHz, The simulator gave the following warning: Quote:    pnoise: freq = 99.96 MHz     (48 %), step = 40 kHz          (2 %) Warning from spectre at freq = 100 MHz during PNoise analysis `pnoise'.    Infinite flicker noise is ignored.    pnoise: freq = 100 MHz       (50 %), step = 40 kHz          (2 %) Is this because 1/f in zero frequency is mixed to 100MHz, and spectreRF can not operate this condition? What I should do next? Thanks a lot! BTW: PNoise analysis is set like this: Quote: pss  pss  fund=100M  harms=20  errpreset=conservative  tstab=20n +    saveinit=yes  annotate=status pnoise  pnoise  start=99M  stop=101M  lin=50  maxsideband=30 +       oprobe=V_MODIFIED  annotate=status

Title: Re: Noise in PFD/CP Post by Andrew Beckett on Nov 1st, 2005, 9:00pm Yes, this is due to the upconverted 1/f noise appearing at multiples of the PSS fundamental - which is of course what would happen in the real circuit. Spectre gives the warning because it can't calculate it exactly at the multiple of the fundamental (because it would be infinite, as the message said). You will of course see a peaking of noise either side of 100MHz, due to the upconverted 1/f noise. Andrew.

Title: Re: Noise in PFD/CP Post by brumby on Nov 1st, 2005, 9:23pm Does it mean that Sn(f) is infinite at frequency  n*fref, . And we should run PNoise simulation from n*fref to (n+1)*fref respectively, and then integrated Sn(f) in these range, and then add them together to get var(n) in equation (57) in Kundert's paper ( phase noise +jitter) Is there some easy way to get var(n), such as select Noise Type in PNoise analysis to be sources, correlation, or modulated?

Title: Re: Noise in PFD/CP Post by tumeda on Nov 10th, 2005, 5:41am Dear Ken, Andrew and all friends, First of all, thanks for so detailed discussion about Pnoise on PFD/CP. But, there are still some unclear to me. For example, the output frequency range of a PLL is 100MHz to 500MHz, the input frequency is 25MHz. Now, i would like to know the noise form CP. The Pnoise simulation is setup according to the above introduction. The input signals are the two pulses signal with an phase offset, which have the same frequency at 25MHz. The output is a grounded voltage source at the 0.5*Vdd. The simulation setup is shown as following: Code: pss  pss  fund=25M  harms=50  errpreset=liberal  tstab=400n +    saveinit=yes  annotate=status pnoise  pnoise  start=10  stop=10G  maxsideband=50  oprobe=V3 +       annotate=status ...." According the formal 56, 57 in the paper "jitter and phase" of Ken, we can calculate the jitter performance of CP. My questions are: 1.  How can I deside the integration range in formal 56 ? In my CP, if the range is from 10Hz to 25MHz, the jitter=36p, while it is from 10Hz to 10G, the jitter = 76p. So the difference is too large. 2. Form the Pnoise of the CP,  I have also a current peak at about 25MHz, which has been also mentioned by others. I think it is simliar to http://www.designers-guide.org/Forum/?board=jitter;action=display;num=1129284499 In the Pnoise curve of my simulation, there is no a noise floor from fc to Nosie Bandwith, which seems to confict with the figure 7 in paper. By the way, How can I know how large is Noise bandwidth for the CP?  and, in Page 28 of the paper, "thus, the noise should be at least 40dB down and dropping at the  highest frequency simulated." This is for phase noise(dBc/Hz) or for output noise (A**2/Hz)??? http://photo.163.com/openpic.php?user=zoujunjx&pid=500381664&_dir=%2F17445359 Any answer would be appreciated!

Title: Re: Noise in PFD/CP Post by jeffyan on Sep 20th, 2007, 2:08am what should we set for the  sweeptype,relative, or absolute? thanks

Title: Re: Noise in PFD/CP Post by rayni on Nov 7th, 2012, 11:00am I have a trouble while simulating the PFD/CP noise. In spectre ADE, if I change the sweep type of analysis pnoise from log to linear, the jitter changes dramatically, from 1xx ps to 2n ps. And with log sweep type, I cannot see the sideband noises spikes at multiple reference frequencies. So, to which sweep type I am supposed to use? Thanks

Title: Re: Noise in PFD/CP (Noise integration range) Post by TheScent on Feb 10th, 2014, 6:50am Dear all, I have another question. I simulated my PFD/CP circuit and got the noise plot, but I cannot set the integration range. Actually, I cannot understand the sentence about integration range in "Predicting the Phase Noise and Jitter of PLL-Based Frequency Synthesizers." Ken said "the noise should be at least 40dB down and dropping at the highest frequency simulated." in the paper. Can anybody tell me about the integration range of my simulated result? I attach the picture of simulation result. Thanks.

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