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Design Languages >> Verilog-AMS >> Export between VHDL-A and Verilog-A models
https://designers-guide.org/forum/YaBB.pl?num=1058190903

Message started by SVT on Jul 14^th, 2003, 6:55am

Title: Export between VHDL-A and Verilog-A models
Post by SVT on Jul 14^th, 2003, 6:55am

Hello all,

May be anybody knows any links to a soft for exporting the VHDL-A models to Verilog-A models? In particularly, I’m interesting the subset of the languages covering the semiconductor devices models.

Thanks for any help!

Sergey.