The Designer's Guide Community Forum

The Designer's Guide Community Forum
https://designers-guide.org/forum/YaBB.pl
Design Languages >> Verilog-AMS >> Cadence-AMS simulator 2.0
https://designers-guide.org/forum/YaBB.pl?num=1071130802

Message started by Guneet Singh on Dec 11^th, 2003, 12:19am

Title: Cadence-AMS simulator 2.0
Post by Guneet Singh on Dec 11^th, 2003, 12:19am

Hello everyone,
I am in the process of setting up the Cadence-AMS 2.0 environment for Verilog-AMS and am facing problems with the cds.lib and hdl.var files.
On debugging the cds.lib file using the 'nchelp -cds.lib' command, I am getting the following error:

ra.ececs.uc.edu ~/verilog11-9> nchelp -cdslib
nchelp: v03.35.(s016): (c) Copyright 1995 - 2002 Cadence Design Systems, Inc.
Parsing -CDSLIB file ./cds.lib.
nchelp: *W,VHCLAF: CDS.LIB (fatal): Syntax error 'DEFINE NCSIMRC ( ./ncsimrc, ~/.ncsimrc )' on line 4 of /opt/CAD/Cadence/AMS-2.0/tools.sun4v/inca/files/hdl.var.
nchelp: *W,VHCLAF: CDS.LIB (fatal): Syntax error 'DEFINE VHDL_SUFFIX ( .vhd, .vhdl )' on line 5 of /opt/CAD/Cadence/AMS-2.0/tools.sun4v/inca/files/hdlvhdl.var.
nchelp: *W,VHCLAF: CDS.LIB (fatal): Syntax error 'DEFINE VERILOG_SUFFIX ( .v )' on line 5 of /opt/CAD/Cadence/AMS-2.0/tools.sun4v/inca/files/hdlvlog.var.

cds.lib files:
1: ./cds.lib
2: /opt/CAD/Cadence/AMS-2.0/tools.sun4v/inca/files/cds.lib
included on line 2 of ./cds.lib
3: /opt/CAD/Cadence/AMS-2.0/tools.sun4v/inca/files/cdsvhdl.lib
included on line 2 of /opt/CAD/Cadence/AMS-2.0/tools.sun4v/inca/files/cds.lib
4: /opt/CAD/Cadence/AMS-2.0/tools.sun4v/inca/files/cdsvlog.lib
included on line 3 of /opt/CAD/Cadence/AMS-2.0/tools.sun4v/inca/files/cds.lib
5: /opt/CAD/Cadence/AMS-2.0/tools.sun4v/inca/files/hdl.var
included on line 3 of ./cds.lib
6: /opt/CAD/Cadence/AMS-2.0/tools.sun4v/inca/files/hdlvhdl.var
included on line 20 of /opt/CAD/Cadence/AMS-2.0/tools.sun4v/inca/files/hdl.var
7: /opt/CAD/Cadence/AMS-2.0/tools.sun4v/inca/files/hdlvlog.var
included on line 21 of /opt/CAD/Cadence/AMS-2.0/tools.sun4v/inca/files/hdl.var

Libraries defined:

Defined in /opt/CAD/Cadence/AMS-2.0/tools.sun4v/inca/files/cdsvhdl.lib:
Line # Filesys Verilog VHDL Path
------ ------- ------- ---- ----
1 std std STD /opt/CAD/Cadence/AMS-2.0/tools.sun4v/inca/files/STD
2 synopsys synopsys SYNOPSYS /opt/CAD/Cadence/AMS-2.0/tools.sun4v/inca/files/SYNOPSYS
3 ieee ieee IEEE /opt/CAD/Cadence/AMS-2.0/tools.sun4v/inca/files/IEEE
4 ambit ambit AMBIT /opt/CAD/Cadence/AMS-2.0/tools.sun4v/inca/files/AMBIT
5 vital_memory vital_memory VITAL_MEMORY /opt/CAD/Cadence/AMS-2.0/tools.sun4v/inca/files/VITAL_MEMORY

Defined in /opt/CAD/Cadence/AMS-2.0/tools.sun4v/inca/files/hdl.var:
Line # Filesys Verilog VHDL Path
------ ------- ------- ---- ----
5 NCHELP_DIR NCHELP_DIR \NCHELP_DIR\ /opt/CAD/Cadence/AMS-2.0/tools.sun4v/inca/files/help

Defined in ./cds.lib:
Line # Filesys Verilog VHDL Path
------ ------- ------- ---- ----
10 worklib worklib WORKLIB ./worklib

I would be grateful if someone could point out the mistake I am making in the whole process.

Thanks and regards,
Guneet

Title: Re: Cadence-AMS simulator 2.0
Post by Andrew Beckett on Dec 22^nd, 2003, 10:51pm

Guneet,

From the error messages, I would guess that you have an INCLUDE or a SOFTINCLUE
in your cds.lib file which is including an hdl.var file. That's not the correct
thing to do. An hdl.var file (whilst similar syntax) needs to be kept separate
from the cds.lib file.

I managed to get similar error messages by doing the above.

You didn't actually post your cds.lib file, so it's hard to be certain, but
this seems a likely explanation to me.

Also, AMS20 is a rather early version of AMS Designer, and I'd definitely
recommend moving to a newer one (e.g. LDV51) if you can. Things have
moved on a lot in AMS Designer.

Regards,

Andrew.

Title: Re: Cadence-AMS simulator 2.0
Post by Guneet Singh on Dec 23^rd, 2003, 1:32am

Mr. Beckett,
Thanks a lot for the responses both here and on the comp.cad.cadence Google group. I am indeed very grateful to you for that.
Regards,
Guneet Singh