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https://designers-guide.org/forum/YaBB.pl Design >> RF Design >> Resistance in CMOS process https://designers-guide.org/forum/YaBB.pl?num=1076376332 Message started by mreja on Feb 9th, 2004, 5:25pm |
Title: Resistance in CMOS process Post by mreja on Feb 9th, 2004, 5:25pm Can someone please provide info. on how to do a layout for P+/N+ silicide RF resistors in CMOS technology. |
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