The Designer's Guide Community Forum https://designers-guide.org/forum/YaBB.pl Design >> RF Design >> Question regarding track and hold model https://designers-guide.org/forum/YaBB.pl?num=1083618111 Message started by gmande on May 3rd, 2004, 2:01pm

 Title: Question regarding track and hold model Post by gmande on May 3rd, 2004, 2:01pm Hello Experts,I have a question regarding track and hold model explained in "Hidden State in SpectreRF" document. Please refer to Section 4, Figure 1 and Listing 2. In listing 2, the veilogA model th contains an internal node hold. V(hold) has been used inside the code. But I am not able to understand where and how the V(hold) value is getting eavaluated.Please let me know if you need more information.Thanks and Regards,Geeta...

Title: Re: Question regarding track and hold model
Post by Andrew Beckett on May 3rd, 2004, 2:45pm

Isn't it fairly clear:

Code:
 // Implement switch with effective series resistence of 1 Ohmif ((\$abstime > tstop – aperture) && (\$abstime <= tstop))  I(hold) <+ V(hold) – V(Pin, Nin);else  I(hold) <+ 1.0e–12 * V(hold);// Implement capacitor with an effective capacitance of tcI(hold) <+ tc * ddt(V(hold));// Buffer outputV(Pout, Nout) <+ V(hold);

The first bit is a switch, which is either a 1 ohm series resistor,
or a leakage resistance of 1 teraohm to ground.
The second is the equation for a capacitor.
And finally V(hold) is used.

With Verilog-A you can write the relationship between currents and voltages - you don't always have to formulate the equation so that the voltage is assigned to.

For example, a resistor can be defined as:

Code:
 I(plus,minus) <+ V(plus,minus)/R;

just as well as:

Code:
 V(plus,minus) <+ I(plus,minus)*R;

both forms are effectively equivalent.

So do you understand now? If not, can you elaborate on what it is you don't understand?

Regards,

Andrew.

 Title: Re: Question regarding track and hold model Post by gmande on May 4th, 2004, 1:03pm Hello Andrew,Thank you so much. Best Regards,Geeta...

 Title: Re: Question regarding track and hold model Post by Eugene on May 4th, 2004, 7:34pm You can also use a resettable integrator that integrates zero. Set the integrate indentically to zero. Insert the input you want to track and hold into the integrator's initial condition. When the integrator's assert input is nonzero, the integrator tracks the time varying initial condition. When the assert input drops to zero, the integrator holds the initial condition. I have used this successfully with SpectreRF.