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Simulators >> Timing Simulators >> How to speed-up the simulation of PLL
https://designers-guide.org/forum/YaBB.pl?num=1128958199

Message started by chip on Oct 10^th, 2005, 2:01am

Title: How to speed-up the simulation of PLL
Post by chip on Oct 10^th, 2005, 2:01am

It's lock time is about 100us
I use nanosim to simulate it,and i set up properly for the trade-pff between accuracy and speed - i think so:)
but the simulation is too slow,as pre-layout simulation,it takes 4 days to finish the simulation about 100us
Can someone guys share some experiences about speed-up the simulation of PLL?

thanks

Title: Re: How to speed-up the simulation of PLL
Post by byang on Oct 10^th, 2005, 8:51am

Chip,

How big is the PLL? How much is the number of device elements? How fast/slow is Spice?

If you put more analog subcircuits into one partition, that might help.

Baolin