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https://designers-guide.org/forum/YaBB.pl Design >> Mixed-Signal Design >> question in sigma-delta ADC https://designers-guide.org/forum/YaBB.pl?num=1135134048 Message started by chuzi on Dec 20th, 2005, 7:00pm |
Title: question in sigma-delta ADC Post by chuzi on Dec 20th, 2005, 7:00pm hi,all i am a beginer in analog ic design and recently in my first project sigma-delta ADC. my case is: 1 bit, cascade 2-1-1modulator, 64 OSR, in simulink SNR could be 108dB, considering KTC noise/clock jitter/nonideal opamp,SNR could be 97dB, noise level is about -140dB. then i begin my circuit. when simulate circuit, it is said noise floor is about -100dB, SNR lower than 80dB, why noise floor is so great? what reason may make this happen? thanks a lot, bow to all:| my opamp(5.6pf load):unitfreq 372Mhz,phasemargin 71.6, gain 97dB,slew rate 280V/us, input noise 5nV/sqr(hz). in simulation, sample rate is 20Mhz, signal i choose 100khz, simulation software is hspice, and VCS(nanosim) thanks |
Title: Re: question in sigma-delta ADC Post by Paul on Dec 20th, 2005, 11:19pm Hi Chuzi, is this a result from FFT after transient analysis? If so, are you sure you sample your output data correctly? You may want to have a look at sheldon's "user's guide" for achieving good FFT measurements: http://www.designers-guide.org/Forum/?board=ms_design;action=display;num=1118555245;start=7#7 The following posts may also be useful: http://www.designers-guide.org/Forum/?board=ms_design;action=display;num=1119874052 Paul |
Title: Re: question in sigma-delta ADC Post by chuzi on Dec 21st, 2005, 5:15pm dear Paul, thanks a lot for the reply, it is my first time to go to forum, and i am very exiting to hear from seniority designer far away, thanks for the guidance:) i always think that there must be something wrong in my fft program, because in my opinion the peak of input signal in spectrum should be narrow, but actually in my result it is very wide. i'd better check it, thanks, it is helpful, i usually cannot find useful resources:) and i am also wandering how to reduce noise floor in circuits:)what reason will lead noise floor become higher? i mean in the same fft program, result from simulink shows noise floor is lower, but result from hspice shows noise floor is higher, does it means my matlab model is not succesful? where should i change?:) and what reason lead this differece?:)thanks:) should i copy simulink graph on forum, that everyone could find my fault easily? thanks again,Paul:) sincerely,chuzi |
Title: Re: question in sigma-delta ADC Post by Paul on Dec 21st, 2005, 11:52pm Chuzi, try to follow the guidelines described in sheldon's post, as well as in the other post mentioned earlier. It should help to reduce both spectral signal width and noise floor. You should be able to get reasonably close to your Matlab results in Spice simulations. Paul |
Title: Re: question in sigma-delta ADC Post by chuzi on Dec 22nd, 2005, 12:57am i see, thanks a lot,Paul :D bow~~~ chuzi :) |
Title: Re: question in sigma-delta ADC Post by sheldon on Dec 22nd, 2005, 6:45am chuzi, Please be aware that the guidelines in the previous append were intended for a Nyquist-rate ADC. A Sigma- Delta ADC has additional requirements. For Nyquist-Rate ADC, we can force the solution to be "periodic" using the method outlined in the post. As a result, spectral leakage is suppressed and the the Rectangular window function can be used. However, a Sigma-Delta ADC has a feedback loop which means that it has memory/ its response is chaotic[non-periodic]/ it has an infinite impulse response. These are different ways of saying you can not entirely suppress the spectral leakage. So you will have to 1) Use a window function for the FFT, I use the Hanning window function. It suppress leakage and does not "smear" the fundamental too much. 2) You may need to run the simulation for two cycles of the fundamental. This improves the resolution bandwidth of the FFT, lowering the noise floor. In addition over two cycles relative effect of the spectral leakage is suppressed. Twice as much signal for the same amount of leakage. Of course more cycles is better, at the cost of extremely long simulation times. 3) You will also need to control the accuracy of the simulator carefully. These designs can have very low noise floors and the simulator accuracy controls need to be set appropriately. Again, the issue is that even simple Sigma-Delta ADC can have very low noise floors. Look at Brian Brandt's papers on Sigma-Delta design from the early 90's, for a second-order ADC, the noise floor is -150dB. Best Regards, Sheldon |
Title: Re: question in sigma-delta ADC Post by chuzi on Dec 22nd, 2005, 10:38pm great thanks! sheldon, under your guidance, my noise floor is reduced about 10dB~20dB, and previous append help me understand simulation tools. thanks a lot!thanks!~~ bow~~ chuzi |
Title: Re: question in sigma-delta ADC Post by chuzi on Dec 28th, 2005, 4:43pm Sheldon and Paul, First,thanks for earlier helps.Under your guidance, I could get SNR to be 92.4dB. My case is: 2-1-1 cascade 1-bit sigma-delta mudolator, 64 oversample ratio. In simulation: 1)11/1024=107.421875KHz sine wave as input, 20MHz sample clock; 2)1024 points fft, 2x simulation time; 3)hanning window is chosen to suppress the spectral leakage; 4)the disadvantage is I used VCS(nanosim) which one has higher speed and lower accuracy. I am going to use hspice which one has higher accuracy but lower speed. Because it will take maybe 2 weeks, I turn to you for some now problem I am not quite sure:) 1)My goal is to simulate the sigma-delta modulator, I just use hspice to simulate the circuits and get the output of the 3 stages, then import it into matlab to finish the error cancellation and decimation. Will this way bring some more error? doing fft in simulation tools could be more accurate or same? I think use more accurate hspice to simulate digital circuit is a waste of time, when I combine analog and digital part, how could I simulate it? 2)I get 2048 points output data and do 1024 points fft, so I chose latter 1024 points, am I right? Did it do some effort to suppress the spectral leakage? 3)Since the noise floor become flater, circuit noise become the major noise. Could you give me same advice on how to suppress the circuit noise? I mean should I make switches to be smaller? How small should I take it? In faster simulation I can hardly tell the diffrence. And how could I change the capacitance? Great thanks and best regards! chuzi |
Title: Re: question in sigma-delta ADC Post by chuzi on Dec 29th, 2005, 1:02am Dear Sheldon, there is another question which bother me. In my fft output figure, distance between the peak of spectrum and the noise floor is over 120dB, but the peak of spectrum is above 120dB and noise floor is about 0dB. Since the input signal should below 0dB, could you be patient to tell me how to get fft figure under 0dB? my .m file is: N=2048; %NP=2048 for mm=1:N OSR64Out(mm)=output64(mm+50); %50 is settle time end figure; w=hann(N); OSR64Outinv=OSR64Out(1:N)'; Osr64outPtot=((abs(fft((OSR64Outinv(1:N).*w)'))).^2/N); Osr64outPtotdB=10*log10(Osr64outPtot); for mm=1:N Pyy(mm)=Osr64outPtot(mm); dbpyy(mm)=Osr64outPtotdB(mm); end CenP=17; %17 is for exclude dc peak maxP=-100; % find peak for i=10:N/2 if dbpyy(i)>maxP maxP=dbpyy(i); CenP=i; end end f=1:N/2; plot(f,dbpyy(1:N/2)); %%%count SNR %%%NOISE Power PNNoDnoise=0;TTP=0;SP=0;THDP=0;PNDnoise=0; for i=20: (N/2) TTP=TTP+Pyy(i); end %%%signal power for i=1:25 %25 is because peak is not narrow enough SP=SP+Pyy(CenP-i+1)+Pyy(CenP+i); end %%%noise PNnoise=TTP-SP; SNR=10*log10(SP/PNnoise) Great thanks and best regards! chuzi |
Title: Re: question in sigma-delta ADC Post by hzheng on Dec 29th, 2005, 1:18am hi chuzi: i have a question about 2-1 sigma-delta modulator behavial model simulation,i use matlab simulink simulation too,but i have bad result PSD,why?can you gave me some advice about it.thank you. |
Title: Re: question in sigma-delta ADC Post by chuzi on Dec 29th, 2005, 4:58pm hi Zheng, I do the same thing as you do, but I don't know where problem is because I can't see your detail. If your modulator is just 2-1 cascade 1-bit, I recommand a reffrence book to you: Shahriar Rabii, Bruce A.Wooley,"The Design of Low-Voltage, Low-Power Sigma-Delta Modulators" Kluwer Academic Publishers. It maybe what you need. Hope it helps. Best regards. chuzi |
Title: Re: question in sigma-delta ADC Post by c.h.zheng on Dec 30th, 2005, 1:29am hi chuzi: thanks for your advice.but i can't find the book that you said,could you gave me the copy of that book to study?thanks !my emial add:wwwhzhenghao@163.com |
Title: Re: question in sigma-delta ADC Post by chuzi on Dec 30th, 2005, 5:18pm hi zhenghao, Your email address is invalid, my deliver failured. My book is borrow from library, and maybe you could find it in your library, it is very useful. In my simulink program, I mainly focus on integrator‘s output, when modifying the scaling factors, first make sure integrator's output not to overload. Hope it helps. Best regards! chuzi |
Title: Re: question in sigma-delta ADC Post by sheldon on Dec 30th, 2005, 6:54pm Chuzi, There is a good description of the factors you might want to explore, at this link http://www.imse.cnm.es/esd-msd/WORKSHOPS/MIXMODEST/PRESENTATIONS/medeiro1.pdf Medeiro has done a good job of breaking down the factors that effect performance. Next, you might want to spend some more time thinking about your overall methodology/strategy for performing this design, in particular, look at the stuff that Ken has written about top-down design. My experience is that using just system level, Simulink, and transistor level simulation is not going to get you the result you want in the time you want. You really need to think about using mixed-level simulation. You will always need to run that final simulation. You just want to run minimize the number of times you run that two week long simulation. Best Regards, Sheldon |
Title: Re: question in sigma-delta ADC Post by c.h.zheng on Jan 1st, 2006, 8:14am hi chuzi: thanks for your advice,my email add:wwwzhenghao@163.com.could you try again,where are you?i'm from chengdu,in china.could you tell me where that book can buy?thanks very much. |
Title: Re: question in sigma-delta ADC Post by chuzi on Jan 3rd, 2006, 7:15pm Dear Sheldon, Great thanks to you for your help, I will read it and think about what you said careful. But maybe I didn't get the exact meaning of your last two sentences,always need to run that final simulation and just want to run minimize the number of times you run that two week long simulation. Could you forgive my ignorance and explain the sentences for me again? Thanks again. And there is another little question:) My fft result is below: The peak signal is above 0dB, my m-file is in earlier post, could you please to tell me how to modify it? Great thanks. Best regards! chuzi sheldon wrote on Dec 30th, 2005, 6:54pm:
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Title: Re: question in sigma-delta ADC Post by chuzi on Jan 3rd, 2006, 7:24pm Hi ZhengHao, I delivered the mail again and I am in BeiJing:) That book is expensive for me, and I suggest that you recommand it to the library nearby and borrow it. That is all about 2-1 cascade 1-bit sigma-delta modulator, you could just follow it. Actually my 2-1-1 followed it,too:) Best regards! chuzi c.h.zheng wrote on Jan 1st, 2006, 8:14am:
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Title: Re: question in sigma-delta ADC Post by material on Jun 4th, 2006, 7:34am It seems that you forget to divide something. You can read the paper "Behavioral Modeling of Switched-Capacitor Sigma–Delta Modulators" CAS,March,03 And the source code which can be found in the mathwork website named SDT for reference. |
Title: Re: question in sigma-delta ADC Post by jovial on Mar 7th, 2016, 10:24pm Hi Sheldon, Can you plz forward me the document since the link does not work . http://www.imse.cnm.es/esd-msd/WORKS...S/medeiro1.pdf |
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