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Design >> RF Design >> Phase Noise of ECL Level Divider
https://designers-guide.org/forum/YaBB.pl?num=1158788102

Message started by timmc6 on Sep 20^th, 2006, 2:35pm

Title: Phase Noise of ECL Level Divider
Post by timmc6 on Sep 20^th, 2006, 2:35pm

Hello,

I am trying to simulate the phase noise of an ECL level divide by 2 circuit. My understanding is that since this circuit is more of an analog circuit and not a CMOS level divider, noise at all time needs to be considered, not just at the midpoint of the transition. So the PNOISE setting should be 'sources' instead of 'time domain'. Is this correct? Also, I am not sure if I should use an 'absolute' sweep or 'relative' sweep in PNOISE. Any thoughts on this are greatly appreciated. Thanks. :)

Regards,
Tim

Title: Re: Phase Noise of ECL Level Divider
Post by Ken Kundert on Sep 20^th, 2006, 8:58pm

Whether the circuit itself is analog or digital is of no consequence. If the ECL divider is followed by another thresholding circuit (such as some form of logic, or the LO input to a mixer), then you should use "time domain" to strobe the noise at the threshold crossings as noise far from the threshold crossings is inconsequential. If instead the divider is driving some other type of circuit (I cannot think of what this might be, perhaps a filter?), then you should use "sources" to compute the time-averaged value for the noise.

-Ken

Title: Re: Phase Noise of ECL Level Divider
Post by timmc6 on Sep 21^st, 2006, 7:40am

Thank you for your response Ken. The ECL level divider I have is driving other ECL dividers, but I need to simulate the phase noise of this one separately from the others. So 'time domain' PNOISE sounds like the way to go. Thanks again.

Tim

Title: Re: Phase Noise of ECL Level Divider
Post by chase.ng on Sep 25^th, 2006, 5:47am

Hi,

What if the divider is driving a switching mixer? Is a switching mixer consider as threholding circuit also?

Thanks,
chase.

Title: Re: Phase Noise of ECL Level Divider
Post by Paul Geraedts on Sep 25^th, 2006, 7:08am

Ken,

The same would apply to the phase noise modelling of a VCO, right? Though the time-averaged phase noise is generally specified. Why? Historic reasons, possibly?

Thanks,

Paul

Title: Re: Phase Noise of ECL Level Divider
Post by Ken Kundert on Sep 25^th, 2006, 11:09am

There are two types of phase variation in oscillators. The dominant source of phase variation is due to oscillator phase noise, which results from noise coupling into the primary oscillation mode. In this case, the phase variation is slow and the same for all signals. In this case, it does not matter if you measure the phase variation at one point in the cycle or time averaged over the whole cycle, because the phase due to this source does not vary significantly over a cycle.

The second source of phase noise is due to sources that are isolated from the primary oscillation mode, such as noise from buffers or dividers. Noise due to these sources are usually modulated by the oscillation signal, in which case they can vary substantially over each cycle, and so should be characterized at the threshold if followed by a thresholding circuit.

And yes, switching mixers are thresholding circuits.

-Ken

Title: Re: Phase Noise of ECL Level Divider
Post by chase.ng on Sep 25^th, 2006, 6:55pm

Hi,

Let say I have a switching up-mixer, and the LO is coming from a divide-by-2. So does it mean the receiver blocking is actually caused by the strobed noise at the mixer threshold?

That means even with VCO, if it is driving a thresholding circuit (like a switching mixer directly), we should still use the time domain noise instead of the time averaged noise, am I right?

Thanks,
chase

Title: Re: Phase Noise of ECL Level Divider
Post by Ken Kundert on Sep 26^th, 2006, 12:06am

I'm saying there are two contributions. At low offset frequencies oscillator phase noise dominates, which does not require the strobed noise. At higher offset frequencies, the divider noise may dominate, in which case you should use the strobed noise.

-Ken

Title: Re: Phase Noise of ECL Level Divider
Post by loose-electron on Sep 27^th, 2006, 8:36pm

Ken:

All good points for inherent noise issues.

I would add some items relative to cross coupling noise that leads to jitter - namely capacitive coupling through bias, power and ground paths.

Suggest running a full LPE on the device and using appropriate impedances in the power and ground of the environment. Also, the power/ground rail noise needs to be modeled.

Jerry

Title: Re: Phase Noise of ECL Level Divider
Post by Paul Geraedts on Sep 28^th, 2006, 6:47pm

Still wondering: how to define noise power without mentioning a time interval? Without a time interval, I don't see how to relate strobed noise and time-averaged noise.

Paul

Title: Re: Phase Noise of ECL Level Divider
Post by Frank Wiedmann on Sep 29^th, 2006, 2:12am

Ken Kundert wrote on Sep 25^th, 2006, 11:09am:

Thanks for this very clear presentation, Ken. Unfortunately, when the people at Cadence implemented the pnoise jitter analysis for autonomous circuits, they seemingly forgot about the second source of phase noise you mention. So, instead of making the pnoise jitter analysis a superset of the pnoise timedomain analysis just like for driven circuits, they made it a superset of the pnoise modulated analysis (for those with SourceLink access, see http://sourcelink.cadence.com/docs/db/kdb/2005/Oct/11196272.html). As far as I understand it, this has the consequence that only the first source of phase noise you mention is taken into account in the simulation. In the setup form for pnoise jitter analysis for autonomous circuits, you can specify neither a circuit node nor a threshold value. In my opinion, this way of implementing the analysis is not very useful because it might neglect important sources of jitter in an autonomous circuit.

Title: Re: Phase Noise of ECL Level Divider
Post by Paul Geraedts on Sep 29^th, 2006, 4:33am

Quote:

As far as I understand it, this has the consequence that only the first source of phase noise you mention is taken into account in the simulation.

I think that's not true. The noise contribution of the circuitry outside the ring of the oscillator (buffer, divider, ...) is still taken into account, although now its noise is time-averaged over a PSS cycle. This seems to result in a *higher* value noise power, see http://www.designers-guide.org/Forum/YaBB.pl?num=1109068827. So the analysis is probably overestimating the noise?

I'm personally still struggling a bit with the word *higher*. I know I tend to confuse continuous time noise with discrete time noise, just like Ken mentions in the post. Though I would like to understand how Spectre calculates the time-averaged noise. Does it do something like a noise analysis at every time point of the PSS and adds these terms together (where every term is a measure of the noise energy in the specific PSS step size)? Or is that a wrong way of looking at it?

Furthermore, is the noise as present during the threshold crossing all phase noise: is there no amplitude noise present? As strobed Pnoise is only looking at one sideband (instead of both and their correlation)!

Thanks very much in advance,

Paul

Title: Re: Phase Noise of ECL Level Divider
Post by Frank Wiedmann on Sep 29^th, 2006, 6:42am

I am not quite sure if the noise contributions from outside the oscillator are taken into account in an averaged way like you say or if it is really only the noise coupling into the primary oscillation mode that is taken into account. Maybe Ken or Andrew can help us out here. However, I feel pretty sure that a better way of implementing the pnoise jitter analysis for autonomous circuits would have been to base it on the pnoise timedomain (or strobed) analysis just like it was done for the driven case.

Regarding the issue of phase noise versus amplitude noise: this was the subject of my very first contribution to this forum, see http://www.designers-guide.org/Forum/YaBB.pl?num=1036850366/.

Title: Re: Phase Noise of ECL Level Divider
Post by Paul Geraedts on Sep 29^th, 2006, 10:46am

Frank,

Thanks for the link you posted. I had not seen it before, and it is very interesting!

Quote:

However, I feel pretty sure that a better way of implementing the pnoise jitter analysis for autonomous circuits would have been to base it on the pnoise timedomain (or strobed) analysis just like it was done for the driven case.

Don't get me wrong: I fully agree with you on this point.

Paul

Title: Re: Phase Noise of ECL Level Divider
Post by Ken Kundert on Sep 29^th, 2006, 9:59pm

In an autonomous PNoise analysis all the noise is accounted for correctly. Thus the noise from both the oscillator and the divider would be included. You can see this if you analyze an oscillator followed by a buffer. If you use SpectreRF to observe the noise at the resonator, you will see that there is no natural noise floor, but if you observe the noise after the buffer there is a noise floor. The noise floor is due to the white noise added by the buffer. The same would be true with a divider. And this also tells you when it would be helpful to use the strobed noise. If you are in the 1/Δf² region, then the noise from the phase mode in the oscillator is dominating. In this case, using strobed noise to determine the phase noise should give the same result as using the time-averaged noise. However, if you are concerned about the noise in the region were it is white or near white, then you would be best served using the strobed noise.

The strobed noise analysis conceptually just adds a sampler to the output of your circuit and then reports on the noise in the resulting sequence. Because it is a discrete-time sequence rather than a continuous time waveform, the spectrum is periodic in f.

You might want to take a look at An Introduction to Cyclostationary Noise, which can be found on http://www.designers-guide.org/Theory/.

-Ken

Title: Re: Phase Noise of ECL Level Divider
Post by Frank Wiedmann on Oct 2^nd, 2006, 1:57am

Ken, just to be clear: I absolutely agree with everything you wrote. As far as I can tell, both the normal and the timedomain/strobed pnoise analyses work absolutely correctly for both driven and autonomous circuits. What I am arguing against is the way the pnoise jitter analysis (which is a relatively new and separate analysis type) is currently implemented for the autonomous case. I do not think that this way is very useful and it would have been much better to implement the pnoise jitter analysis for autonomous circuits in just the same way as for driven circuits.

Title: Re: Phase Noise of ECL Level Divider
Post by Ken Kundert on Oct 2^nd, 2006, 8:22am

I understand. I have not seen this newer version yet, but I'll make sure that Cadence reads this thread.

-Ken

Title: Re: Phase Noise of ECL Level Divider
Post by Vick on Oct 6^th, 2006, 6:04am

[quote author=timmc6 link=1158788102/0#0 date=1158788102]Hello,

Also, I am not sure if I should use an 'absolute' sweep or 'relative' sweep in PNOISE.

Hy! I'm still waiting for an answer to this question, relative or absolute? It seems to me that an Absolute Sweeptype is equivalent to a Relative one with Relative Harmonic parameter set to 0. And I think that this is the correct way of predicting the noise near the main output frequency (Is that so?). Then why some people suggests as the correct Relative Harmonic = 1 in the pnoise form of Spectre?
Thanks.

Title: Re: Phase Noise of ECL Level Divider
Post by Ken Kundert on Oct 6^th, 2006, 10:17am

If you are using strobing, it does not matter as the noise is periodic in frequency.

-Ken

Title: Re: Phase Noise of ECL Level Divider
Post by neoflash on Jul 5^th, 2011, 10:54am

Ken,

When you mention strobed analysis, you mean noisetype = "time-domain" or "jitter" ?

Ken Kundert wrote on Oct 6^th, 2006, 10:17am:

If you are using strobing, it does not matter as the noise is periodic in frequency.

-Ken

Title: Re: Phase Noise of ECL Level Divider
Post by Ken Kundert on Jul 5^th, 2011, 10:31pm

Yes.

Title: Re: Phase Noise of ECL Level Divider
Post by neoflash on Jul 5^th, 2011, 10:35pm

Ken,

It is actually a selective question. noisetype = "time domain" or "jitter".

:D

Title: Re: Phase Noise of ECL Level Divider
Post by Frank Wiedmann on Jul 6^th, 2011, 12:52am

For pnoise analysis, the timedomain and jitter noisetypes (PM jitter for autonomous circuits) are almost identical. The only difference is how you specify the strobing times. In general, noisetype=pmjitter is more useful because you specify the times by using threshold crossings. The noisetype=timedomain is the older variant, there you specify the times with respect to the result of the pss analysis.

Title: Re: Phase Noise of ECL Level Divider
Post by neoflash on Jul 6^th, 2011, 11:02am

Thanks for the comments.

I'm surprised that Cadence's documentation is so weak on this topic. And users have to go beyond their website to understand this basic usage information.

At least, they should provide application notes for VCO, driven circuits and PFD/CP. The step by step setup procedures and result processing.

Frank Wiedmann wrote on Jul 6^th, 2011, 12:52am:

Title: Re: Phase Noise of ECL Level Divider
Post by neoflash on Jul 6^th, 2011, 11:25am

Removed wrong question.

Title: Re: Phase Noise of ECL Level Divider
Post by neoflash on Jul 6^th, 2011, 12:01pm

When I was trying to convert the Jee (Sec/Hz) in "PM jitter" mode to phase noise in "source" mode, I found they are nicely offset by 112dBc.

I was using below equation for this conversion:

multiple Jee with term "sqrt( 2*pai*Fo )" and do 20*log10() to get the expected phase noise curve.

However, the calculated from Jee is 112dB lower than phase noise from source mode. I'm not sure which step go wrong.

- Neo

Title: Re: Phase Noise of ECL Level Divider
Post by Frank Wiedmann on Jul 6^th, 2011, 3:03pm

Have you carefully read the thread at http://www.designers-guide.org/Forum/YaBB.pl?num=1224609785 ? You will probably find the answers to most of your questions there.

Title: Re: Phase Noise of ECL Level Divider
Post by neoflash on Jul 6^th, 2011, 4:25pm

Oops. Correct equation but one term square rooted by mistake.

It turns out that Jee converted will be DSB while source mode is SSB. Jee is 3dB higher.

I think Cadence should follow the same guideline for DSB and SSB for all modes.