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Design Languages >> Verilog-AMS >> Limitation with Cadence AMS designer suite
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Message started by shaikh_sarfraz on Oct 22^nd, 2007, 11:12pm

Title: Limitation with Cadence AMS designer suite
Post by shaikh_sarfraz on Oct 22^nd, 2007, 11:12pm

Hi All,
Presently it has been seen that many of the syntax given in Verilog-AMS language is not supported by Cadence AMS designer. Like realtobits and bitstoreal operator which are supported in Verilog-D are not supported in Verilog-AMS.

Here is my problem statement:
Presently I am modelling a sensor block. I have to model a block which reads a 2 dimnesional array of reg data then convert it into real/electrical and send it to the output port.

Since in Verilog-D we cannot declare output port as real, so I migrated to Verilog-AMS so that the real data can be sent to the output port (I am assuming electrical ports can be assigend real values).

However during compilation stage it is giving the error that "$bitstoreal is not supported by Affirma-AMS"

Can any body suggest some owrk around?

Regards
Sarfraz

Title: Re: Limitation with Cadence AMS designer suite
Post by Ken Kundert on Oct 23^rd, 2007, 1:42pm

I believe I have used $realtobits in AMS Designer in a digital context. I suspect that it would not work if you used $realtobits in the analog section.

-Ken