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Design >> Analog Design >> CMRR in a r2r input stage
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Message started by filipe on Feb 14^th, 2008, 2:31pm

Title: CMRR in a r2r input stage
Post by filipe on Feb 14^th, 2008, 2:31pm

What is the best choice in rail-to-rail input stages, concerning the CMRR in all the range of operation????
Because in the transition region, the CMRR are degraded a lot using complementary differential pairs.
What could be a good topology to overcome this problem?
Thanks a lot!
Filipe

Title: Re: CMRR in a r2r input stage
Post by vivkr on Feb 14^th, 2008, 11:05pm

The good question to ask would be: Do I need an input R2R amp or is it possible to make some changes at the system level to avoid this?
I doubt if you will find an input R2R stage which does not suffer from CMRR issues. There are some papers where they suggest using
a PMOS + NMOS input pair such that the total current through both is kept constant at all input levels and the transistor are in weak inversion.
The same would be true if you were to use NPN and PNP input pairs.

However, if you opt for input R2R, you more or less have to live with poor CMRR, unless you artificially increase your linear input range by
using a chargepump to boost the internal VDD for instance. Then, you could use just a standard diff pair. See the JSSC paper by Duisters and Dijkman
(Philips).

Regards
Vivek

Title: Re: CMRR in a r2r input stage
Post by thechopper on Feb 18^th, 2008, 4:50pm

Hi filipe,

What Vivek pointed out is true. However, you might still want to take a peek at this reference "Constant-gm Constant-Slew-Rate High-Bandwidth Low-Voltage Rail-to-Rail CMOS Input Stage for VLSI Cell Libraries" Juan M. Carrillo, J. Francisco Duque-Carrillo, Guido Torelli and José L. Ausín. JSSC Aug 2003. This is an all-NMOS r2r input. Although not specifically designed for improving CMRR, it might be better than the usual complementary pair.

Tosei