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Modeling >> Passive Devices >> RF modeling of varactor in tsmc .18 process
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Message started by neoflash on Apr 7^th, 2008, 7:12am

Title: RF modeling of varactor in tsmc .18 process
Post by neoflash on Apr 7^th, 2008, 7:12am

Hi, folks:

I have a question on the modeling of RF varactors (nmos in nwell) in TSMC 0.18um RF PDK.

If we take a look at the RF model, we will find that Rg and Rds element is in series with the variable capacitor. However, I'm not sure whether it fully modeled the loss of the varactor.

1. the Rg and Rds is not related to Vgb of the varactor. This doesn't match the reality that changing the Vgd will change the series resistance of Nwell.

2. I'm not sure how well it is correlated with measurement.

Since I will use the varactor in very high frequency VCO (10g), and the quality factor of the varactor is very important. Please comment on this.

Title: Re: RF modeling of varactor in tsmc .18 process
Post by didac on Apr 7^th, 2008, 12:13pm

Hi,
Have you checked the process characterization report-or the name that TSMC gives to it-?, in this document should be data about the error between the model and the measurements and up to which frequency it was measured, in the 0.18um process that I'm using(not TSMC) 10GHz was included in the model according to this report.
Hope it helps,

Title: Re: RF modeling of varactor in tsmc .18 process
Post by neoflash on Apr 8^th, 2008, 5:07am

didac wrote on Apr 7^th, 2008, 12:13pm:

Thanks for the reply.

However, this lead to another question. Designing a VCO in 10G may have a resonant tank's Q dominated by the varactor. This varactor might not be very well modeled, so that the tank impedance at resonance is hard to model.

How can I make sure it will start-up and how much current should I feed...? Tough.

Title: Re: RF modeling of varactor in tsmc .18 process
Post by didac on Apr 8^th, 2008, 7:41am

Hi,
It's a difficult situation if you can't trust the model...maybe you can contact the foundry an see what they tell, or provide overdesign(i.e. design with the model and allow trimming to vary the current just in case), the third alternative that I can think about it's a "little"-in fact it's a big amount of work- bit of reverse engineering like trying to build your own varactor(replicate foundry model) using something like ATLAS from Silvaco (http://www.silvaco.com/products/device_simulation/atlas.html)(I think Synopsys have a similar physical modelling tool) and then use a tool to generate the model(I don't know if ATLAS supports this, maybe IC-CAP from Agilent it's necessary), the problem is that beeing a physics modelling approach it's necessary to have data from the process(doping profiles basically) and obtaining from known electrical parameters could be difficult or impossible.
Hope it helps,

Title: Re: RF modeling of varactor in tsmc .18 process
Post by love_analog on Apr 27^th, 2010, 9:32pm

neoflash,
just put an AAC loop so that you will get extra current to make sure oscillations start but then the current wll decrease to get you to the correct voltage amplitude (so that you are in the current limited regime).
This answers your question on startup.

For phase noise, its more difficult. You need to make sure the process is mature enough and the model does fit the measurement well enough