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Analog Verification >> Analog Functional Verification >> Question on Mixed-signal fullchip verification
https://designers-guide.org/forum/YaBB.pl?num=1237389590

Message started by pip9ball on Mar 18^th, 2009, 8:19am

Title: Question on Mixed-signal fullchip verification
Post by pip9ball on Mar 18^th, 2009, 8:19am

Hello everyone,

I just stumbled across this site and I think this is a great find! I am a Design automation engineer whose background is primarily in digital front-end and physical implementation. Due to some reorganization I have been asked to develop/support a fullchip mixed signal flow. Our current flow uses several custom brewed skill/perl scripts to generate a VHDL on top netlist. This flow was written by an Design engineer who is longer with the company and whose code is extremely hard to follow.

Our company uses vhdl-ams to model analog circuits and I am struggling to find a EDA solution that will netlist a fullchip design with some blocks being vhdl-ams.

Fullchip mixed signal validation is very new to me and I was hoping some experts on this board can steer me in the right direction.

Thanks and regards,

Phil

Title: Re: Question on Mixed-signal fullchip verification
Post by Ken Kundert on Mar 18^th, 2009, 5:11pm

Cadence: AMS-Designer
Mentor: Advance-MS

Perhaps Dolphin?

-Ken

Title: Re: Question on Mixed-signal fullchip verification
Post by Visjnoe on Mar 19^th, 2009, 12:55am

Synopsys: Discovery-AMS

Kind Regards

Peter

Title: Re: Question on Mixed-signal fullchip verification
Post by jbdavid on Mar 19^th, 2009, 10:17am

Our house uses some VHDL on the digital side, on the analog side we use primarily Verilog | Verilog-AMS and Verilog-A..

If Cadence Virtuoso is your analog design environment, they have an excellent mixed signal simulation environment, if expensive. Many other simulators are supported in that environment too.. but the VHDL-AMS subset supported in the netlister had been somewhat limited to a subset of that language that was compatible with Verilog-AMS, and it was typically Verilog on top.. BUT My knowledge of all the workable permuations of that tool is out of date, so I'd talk to your cadence AE to see what they support... if you are using cadence icfb tools.

But you don't explain what design database type you are trying to use, so it's hard to make any suggestions.

Jonathan

Title: Re: Question on Mixed-signal fullchip verification
Post by jbdavid on Nov 11^th, 2010, 12:01am

if you are on a recent fedora or releated linux release, you can use

yum groupinstall 'Electronic Lab'
to get a full set of opensource design tools including ngspice (which claims verilog-a support) and gnucap as well as icarus verilog which supports real number modeling.

or you can get the liveDVD at http://spins.fedoraproject.org/fel/
and do a fresh install.