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Analog Verification >> Analog Functional Verification >> Analog Verification in a SOC

Message started by Nirav Desai on Dec 4th, 2009, 8:57am

Title: Analog Verification in a SOC
Post by Nirav Desai on Dec 4th, 2009, 8:57am

I just finished reading the article on Analog Verification in a System on Chip ( in IEEE Solid State Circuits Magazine Fall 2009 ) and found the approach described very interesting. I think the authors missed one aspect of mixed signal simulation in their approach.

As I understand from the example on the Equalizer, you write the Verilog AMS code for the equalizer and interface it with the Analog Circuit at the Model Level only ( not the schematic transistor level ).

Now for high speed digital logic, the transitions from the digital logic will couple to the analog portions of the circuit through the parasitic capacitance of the transistor, interconnect and the substrate. This will corrupt the analog output and may cause digitizing errors in subsequent blocks. Only a combined transient simulation ( of analog and digital combined ) will capture this effect. So a transient simulation at the schematic level for the analog and digital sections interfaced will still be necessary. If the noise margins for the subsequent blocks are known beforehand, interfacing between different blocks may be avoided by calculating the glitches in the output of the analog blocks.

Title: Re: Analog Verification in a SOC
Post by Nirav Desai on Dec 4th, 2009, 12:19pm

I forgot to mention the effect of direct coupling from the control word change to the analog block output.

Title: Re: Analog Verification in a SOC
Post by jbdavid on Dec 6th, 2009, 2:47pm

I've not (yet) read the article.. but as a practitioner in this area, I'll say that you're correct. Parasistic coupling effects, like gate delays, are not part of the domain of functional verification, and you do need OTHER analyses to find these issues. The point of functional verification is to make sure to catch the stupid connection issues that would prevent you from running the first part on the test bench to discover that you might have a parasitic issue.
Functional verification is NOT going to find this issue, but it will catch most of the REST of the design bugs so that when you do run that transistor extracted simulation, you can let it run to the point where the subtle issues can be identified.  Its really hard to do that, if there are 20 design bugs to find and fix in a 10day simulation, unless you have a great foosball table, and six months of funding to burn. (imagining that once in a while you'll be able to fix two bugs before the next run.)


Title: Re: Analog Verification in a SOC
Post by ywguo on Jan 17th, 2010, 6:50pm

Hi Guys,

I read that article ( in IEEE Solid State Circuits Magazine Fall 2009 ), too. It interests me very much.

Is this method for functional verification of SoC only? Can we use it to define a suite of testbench to check if the design (like a PLL or a ADC) comply with the requirements in specifications?

For example, the simplest is some DC parameters like bandgap voltage, average power consumption, and so on. The more complex parameters including some dynamic performance of ADC.

Any comments are appreciated.

Best Regards,

Title: Re: Analog Verification in a SOC
Post by Nirav Desai on Jan 17th, 2010, 9:13pm

Hi Yawaei. As I understand, the described methodology uses behavioral models for core analog circuits and then combines them with Verilog AMS based models for the digital circuits to the verification.

For PLLs and ADCs which have an inherent analog functionality, you will have to do a transient simulation to capture all the charge sharing / pumping and coupling effects. Once all specs have been checked for, you may try to build a behavioral model which can then be coupled with Verilog AMS based models for the subsequent parts in the chain. The accuracy of system simulation will be determined by how close your behavioral models are to the actual transient simulation.

Title: Re: Analog Verification in a SOC
Post by ywguo on Jan 17th, 2010, 11:02pm


Refer to that article.

Another interesting side effect
of adopting analog verification is
that it tends to lead to healthier
design teams. Analog verification
provides a safety net that catches
the errors of inexperienced design
engineers, making it possible to
build design teams from designers
that have a range of experience
levels. No longer is it necessary for
a design group to limit itself to hiring
only design engineers with many
years experience. Analog verification
thus greatly increases the pool of
available engineers. It allows engineers
to develop naturally in a company
and encourages them to stay
with the company.

If there is a language which can describe the specification exhaustively and capture all subtle issues, probably it will help analog designers clear all potential risks.


Title: Re: Analog Verification in a SOC
Post by jbdavid on Nov 10th, 2010, 11:56pm

this sort of functional verification doesn't lend itself to Performance verification.. so the designer will STILL need to run circuit level spice analysis, but designers test bench typically doesn't test ALL the inputs, but rather each sim focuses on a specific normal mode of operation and measures the circuit performance in the mode.
Its the functional verification that will tell you that the bias current is wrong, or the control was inverted from what the design expected!

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